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1. 发明授权

US08135942B2 System and method for double-issue instructions using a dependency matrix and a side issue queue 失效
标题翻译：使用依赖关系矩阵和侧面问题队列的双重指令的系统和方法
公开(公告)号：US08135942B2
公开(公告)日：2012-03-13
申请号：US12199971
申请日：2008-08-28
申请人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton , John B. Griswell, Jr.
发明人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton , John B. Griswell, Jr.
IPC分类号： G06F9/50 , G06F9/52 , G06F9/312
CPC分类号： G06F9/30145 , G06F9/3838 , G06F9/3842 , G06F9/3885
摘要： A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method places the second portion into a side issue queue. The method issues the second portion when the side issue queue indicates that the second portion is eligible for issue.
摘要翻译：一种方法接收包括第一部分和第二部分的复杂指令。该方法设置单个问题队列插槽，并为复杂指令分配执行单元，并识别第一和第二部分的依赖关系。该方法为第一和部分部分设置依赖矩阵槽和消费者表槽。在满足第一部分依赖性的情况下，该方法发出第一部分，然后从单个问题队列插槽中发出第二部分。在第二部分依赖性尚未得到满足的情况下，该方法将第二部分放置在侧面发布队列中。当侧面发出队列指示第二部分有资格发行时，该方法发出第二部分。

2. 发明申请

US20100058033A1 System and Method for Double-Issue Instructions Using a Dependency Matrix and a Side Issue Queue 失效
标题翻译：使用依赖矩阵和边问题队列的双重问题指令的系统和方法
公开(公告)号：US20100058033A1
公开(公告)日：2010-03-04
申请号：US12199971
申请日：2008-08-28
申请人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton , John B. Griswell, JR.
发明人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton , John B. Griswell, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3838 , G06F9/3842 , G06F9/3885
摘要： A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method places the second portion into a side issue queue. The method issues the second portion when the side issue queue indicates that the second portion is eligible for issue.
摘要翻译：一种方法接收包括第一部分和第二部分的复杂指令。该方法设置单个问题队列插槽，并为复杂指令分配执行单元，并识别第一和第二部分的依赖关系。该方法为第一和部分部分设置依赖矩阵槽和消费者表槽。在满足第一部分依赖性的情况下，该方法发出第一部分，然后从单个问题队列插槽中发出第二部分。在第二部分依赖性尚未得到满足的情况下，该方法将第二部分放置在侧面发布队列中。当侧面发出队列指示第二部分有资格发行时，该方法发出第二部分。

3. 发明申请

US20100257341A1 Selective Execution Dependency Matrix 审中-公开
标题翻译：选择性执行依赖矩阵
公开(公告)号：US20100257341A1
公开(公告)日：2010-10-07
申请号：US12417801
申请日：2009-04-03
申请人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
发明人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell. A second read port couples to the first array and comprises a second read wordline and a second read bitline. The second read wordline couples to the second latch and the first column and asserts a second available signal based on the second bit. The second read bitline couples to the first row and generates a second ready signal based on the second read wordline and the first cell.
摘要翻译：具有依赖矩阵的处理器包括第一阵列，其包括以多个列排列的多个单元和多个行。每行表示处理器执行队列中的指令，每个单元表示处理器执行队列中的两个指令之间的依赖关系。第一锁存器耦合到第一阵列并且包括第一位，第一位指示第一状态。第二锁存器耦合到第一阵列并且包括第二位，第二位指示第二状态。第一读取端口耦合到第一阵列，包括第一读取字线和第一读取位线。第一读取字线耦合到第一锁存器和第一列，并基于第一位置位第一可用信号。第一读取位线耦合到第一行并且基于第一可用信号和第一单元产生第一就绪信号。第二读取端口耦合到第一阵列并且包括第二读取字线和第二读取位线。第二读取字线耦合到第二锁存器和第一列，并基于第二位置位第二可用信号。第二读取位线耦合到第一行，并且基于第二读取字线和第一单元产生第二就绪信号。

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