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1. 发明授权

US07027130B2 Device and method for determining an illumination intensity profile of an illuminator for a lithography system 有权
标题翻译：用于确定光刻系统的照明器的照明强度分布的装置和方法
公开(公告)号：US07027130B2
公开(公告)日：2006-04-11
申请号：US10833651
申请日：2004-04-28
申请人： Christopher A. Spence , Todd P. Lukanc , Luigi Capodieci , Joerg Reiss , Sarah N. McGowan
发明人： Christopher A. Spence , Todd P. Lukanc , Luigi Capodieci , Joerg Reiss , Sarah N. McGowan
IPC分类号： G03B27/72
CPC分类号： G03F7/7085 , G03F7/70133 , G03F7/70441 , G03F7/70666 , G03F7/70941
摘要： A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.
摘要翻译：一种用于产生形成投影光刻系统的一部分的照明器的照明强度分布的系统和方法。来自照明器的辐射被投射到具有多个孔的照明轮廓掩模，使得每个孔通过辐射的不同部分。检测并组装每个不同部分的辐射的强度以形成照射强度分布。

2. 发明授权

US07071085B1 Predefined critical spaces in IC patterning to reduce line end pull back 有权
标题翻译： IC图案化中预定的关键空间，以减少线端拉回
公开(公告)号：US07071085B1
公开(公告)日：2006-07-04
申请号：US10852876
申请日：2004-05-25
申请人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
发明人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
IPC分类号： H01L21/475
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , Y10S438/947
摘要： The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.
摘要翻译：本发明包括一种制造这种设备的装置和方法，包括以下步骤：形成待图案化的层，在待图案化的层上形成感光层，使光敏层形成图案，形成包括水平线和垂直线将图案转移到待图案化的层上，在图案上形成第二感光层，图案化第二感光层以形成包括在水平线和垂直线之间对准的空间的第二图案，并且转印第二图案到要被图案化的层以形成包括水平线和在其间具有空间的垂直线的第三图案，该空间包括在光刻的分辨率极限下可实现的宽度尺寸。

3. 发明授权

US07015148B1 Reduce line end pull back by exposing and etching space after mask one trim and etch 有权
标题翻译：通过在掩模一次修整和蚀刻后曝光和蚀刻空间来减少线端拉回
公开(公告)号：US07015148B1
公开(公告)日：2006-03-21
申请号：US10852883
申请日：2004-05-25
申请人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
发明人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0276 , H01L21/28123 , H01L21/28282 , H01L21/32139
摘要： The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.
摘要翻译：本发明是制造半导体器件和这种半导体器件的方法。半导体器件包括集成电路图案，其包括水平线，垂直线和它们之间的空间，该空间包括精确的宽度尺寸。该方法包括以下步骤：形成待图案化的感光层，图案化感光层以形成包括主水平线和主垂直线的图案，其间没有间隙，使用图案化将图案转移到至少一个下层在所述图案化的至少一个下层上形成第二感光层，对所述第二感光层进行图案化，以形成第二图案，所述第二图案包括对准以剖开在所述至少一个下层中形成的水平线和垂直线的主空间，以及将所述第二图案转移到所述至少一个下层，以形成包括水平线和在其间具有空间的垂直线的第三图案，所述空间包括精确的宽度尺寸。

4. 发明授权

US07269804B2 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US07269804B2
公开(公告)日：2007-09-11
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

5. 发明授权

US07543256B1 System and method for designing an integrated circuit device 失效
标题翻译：用于设计集成电路器件的系统和方法
公开(公告)号：US07543256B1
公开(公告)日：2009-06-02
申请号：US10790590
申请日：2004-03-01
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F8/48 , G06F8/447 , G06F17/5022
摘要： A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.
摘要翻译：一种方法包括提供初始的IC器件设计，该设计具有期望的一组电特性。生成对应于初始设备设计的布局表示。仿真工具用于确定布局表示是否对应于具有所需电气特性的IC器件设计。此外，使用仿真工具评估由于工艺变化而设计的IC器件内的结构之间的变化。该变体可用于确定设计是否被优化。

6. 发明授权

US07207017B1 Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results 有权
标题翻译：计量配方生成方法和系统，设计，模拟和计量结果的审查和分析
公开(公告)号：US07207017B1
公开(公告)日：2007-04-17
申请号：US10865047
申请日：2004-06-10
申请人： Cyrus Tabery , Chris Haidinyak , Todd P. Lukanc , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus Tabery , Chris Haidinyak , Todd P. Lukanc , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.
摘要翻译：生成计量配方的方法包括识别设备布局内的感兴趣区域。可以提供对应于所识别的感兴趣区域的坐标列表并用于创建剪切布局，其可以由剪切布局数据文件表示。裁剪的布局数据文件和相应的坐标列表可以被提供并转换成用于在测试处理的晶片和/或掩模版时引导一个或多个计量仪器的计量配方。根据测量要求收到的实验测量结果可以与相应的设计数据和仿真数据相关联，并存储在可数据库系统中。

7. 发明授权

US07657864B2 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US07657864B2
公开(公告)日：2010-02-02
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

8. 发明授权

US07194725B1 System and method for design rule creation and selection 失效
标题翻译：设计规则创建和选择的系统和方法
公开(公告)号：US07194725B1
公开(公告)日：2007-03-20
申请号：US10817132
申请日：2004-04-02
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.
摘要翻译：一种产生设计规则的方法，包括生成多个参数变化的几何布局并且模拟每个几何布局如何在晶片上图案化。模拟几何布局中的结构边缘可以基于可制造性进行分类，并且可以创建设计规则以禁止展示不良制造性的布局。

9. 发明授权

US07313769B1 Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
标题翻译：通过考虑布局交互以及额外的可制造性边际来优化集成电路布局
公开(公告)号：US07313769B1
公开(公告)日：2007-12-25
申请号：US10790381
申请日：2004-03-01
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.
摘要翻译：产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

10. 发明授权

US06974652B1 Lithographic photomask and method of manufacture to improve photomask test measurement 失效
标题翻译：平版印刷光掩模和制造方法以改进光掩模测试测量
公开(公告)号：US06974652B1
公开(公告)日：2005-12-13
申请号：US10699748
申请日：2003-11-03
申请人： Todd P. Lukanc , Luigi Capodieci , Bhanwar Singh , Christopher A. Spence
发明人： Todd P. Lukanc , Luigi Capodieci , Bhanwar Singh , Christopher A. Spence
IPC分类号： G01F9/00 , G03F1/00 , G03F1/08 , G03F1/14
CPC分类号： G03F1/40 , G03F1/58 , G03F1/86
摘要： A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.
摘要翻译：公开了用于光刻工艺的光掩模和制造光掩模的方法。可以提供包括衬底，设置在衬底上的牺牲导电层和设置在牺牲导电层上方的辐射屏蔽层的掩模坯料。然后从辐射屏蔽层形成结构以限定图案。使用测量工具测量与结构相关的参数，并且在测量期间，牺牲导电层提供导电平面以消散由测量工具传递到掩模的电荷。

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