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1. 发明授权

US08788891B2 Bitline deletion 失效
标题翻译：位线删除
公开(公告)号：US08788891B2
公开(公告)日：2014-07-22
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/00 , G11C29/00 , G06F11/10 , G11C29/12
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

2. 发明申请

US20130339808A1 BITLINE DELETION 失效
公开(公告)号：US20130339808A1
公开(公告)日：2013-12-19
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/20
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

3. 发明申请

US20110320919A1 HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE 失效
标题翻译：高性能缓存目录错误修正代码
公开(公告)号：US20110320919A1
公开(公告)日：2011-12-29
申请号：US12822889
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/1064 , H03M13/19
摘要： Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.
摘要翻译：定义一组可纠正的错误和不可校正的错误校正码代码点，产生纠错码（ECC）校正码解码，关于不可校正的错误校正码码点为“不关心”，并在逻辑上最小化ECC校验码解码以确定基于关于不可校正误差校验码码点的可校正误差校验码码点作为“不关心”，由此对于不可校正的误码校验码码点可以忽略输出数据。

4. 发明申请

US20110320732A1 USER-CONTROLLED TARGETED CACHE PURGE 失效
标题翻译：用户控制的高速缓存池
公开(公告)号：US20110320732A1
公开(公告)日：2011-12-29
申请号：US12822428
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/126
摘要： User-controlled targeted cache purging includes receiving a request to perform an operation to purge data from a cache, the request including an index identifier identifying an index associated with the cache. The index specifies a portion of the cache to be purged. The user-controlled targeted cache purging also includes purging the data from the cache, and providing notification of successful completion of the operation.
摘要翻译：用户控制的目标缓存清除包括接收执行从缓存清除数据的操作的请求，所述请求包括标识与高速缓存相关联的索引的索引标识符。该索引指定要清除的缓存的一部分。用户控制的目标缓存清除还包括从缓存中清除数据，并提供成功完成操作的通知。

5. 发明授权

US08365055B2 High performance cache directory error correction code 失效
标题翻译：高性能缓存目录纠错码
公开(公告)号：US08365055B2
公开(公告)日：2013-01-29
申请号：US12822889
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, Jr.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, Jr.
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1064 , H03M13/19
摘要： Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.
摘要翻译：定义一组可纠正的错误和不可纠正的错误校正码代码点，生成关于不可校正错误校验码码点的纠错码（ECC）校验码解码，因为不考虑和逻辑地最小化用于确定可纠正错误的ECC校验码解码基于关于不可校正误差校正码码点的校验码码点，因为不需要关心的输出数据可以被忽略用于不可校正的误码校验码码点。

6. 发明授权

US08364899B2 User-controlled targeted cache purge 失效
标题翻译：用户控制的目标缓存清除
公开(公告)号：US08364899B2
公开(公告)日：2013-01-29
申请号：US12822428
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, Jr.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, Jr.
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/126
摘要： User-controlled targeted cache purging includes receiving a request to perform an operation to purge data from a cache, the request including an index identifier identifying an index associated with the cache. The index specifies a portion of the cache to be purged. The user-controlled targeted cache purging also includes purging the data from the cache, and providing notification of successful completion of the operation.
摘要翻译：用户控制的目标缓存清除包括接收执行从缓存清除数据的操作的请求，所述请求包括标识与高速缓存相关联的索引的索引标识符。该索引指定要清除的缓存的一部分。用户控制的目标缓存清除还包括从缓存中清除数据，并提供成功完成操作的通知。

7. 发明申请

US20130339811A1 BITLINE DELETION 有权
公开(公告)号：US20130339811A1
公开(公告)日：2013-12-19
申请号：US13523624
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/1064 , G06F12/0802 , G11C29/702 , G11C2029/0409 , G11C2029/0411 , G11C2029/1204
摘要： Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.
摘要翻译：基于在所选择的位线地址检测高速缓存中的高位线错误率条件，其中高位线错误率条件指示所选位线地址处的高错误率，激活可编程切换缓存。该方法还包括基于可编程开关被激活并遇到与所选择的位线地址相关联的错误，由计算机系统自动地删除与高速缓存中的后续错误相关联的一个或多个高速缓存行，而不管随后的地址如何基于激活的可编程开关的错误，其中自动线删除指示线不可用。

8. 发明授权

US08595570B1 Bitline deletion 有权
标题翻译：位线删除
公开(公告)号：US08595570B1
公开(公告)日：2013-11-26
申请号：US13523624
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney
IPC分类号： G06F11/27 , G06F11/32
CPC分类号： G06F11/1064 , G06F12/0802 , G11C29/702 , G11C2029/0409 , G11C2029/0411 , G11C2029/1204
摘要： Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.
摘要翻译：基于在所选择的位线地址检测高速缓存中的高位线错误率条件，其中高位线错误率条件指示所选位线地址处的高错误率，激活可编程切换缓存。该方法还包括基于可编程开关被激活并遇到与所选择的位线地址相关联的错误，由计算机系统自动地删除与高速缓存中的后续错误相关联的一个或多个高速缓存行，而不管随后的地址如何基于激活的可编程开关的错误，其中自动线删除指示线不可用。

9. 发明授权

US07502986B2 Method and apparatus for collecting failure information on error correction code (ECC) protected data 有权
标题翻译：收集有关纠错码（ECC）保护数据的故障信息的方法和装置
公开(公告)号：US07502986B2
公开(公告)日：2009-03-10
申请号：US11054575
申请日：2005-02-09
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result, decoding flipped data bits, processing the received data and the decoded flipped bits to correct the data, outputting corrected data having an ECC, receiving a trap update signal, and saving the decoded flipped data bits responsive to receiving the trap update signal.
摘要翻译：一种用于系统的纠错码（ECC）调试的方法，包括：接收具有ECC的数据，确定是否已经发生数据错误，产生错误结果的综合征，翻转翻转的数据位，处理接收的数据和解码的翻转的位校正数据，输出具有ECC的校正数据，接收陷阱更新信号，以及响应于接收到陷阱更新信号而保存解码翻转数据位。

10. 发明授权

US08914708B2 Bad wordline/array detection in memory 有权
标题翻译：内存中的字线/阵列检测不良
公开(公告)号：US08914708B2
公开(公告)日：2014-12-16
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： G11C29/00 , H03M13/05 , G06F11/07 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.
摘要翻译：提供了一种错误检测技术。控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。控制器检测读取的字线的ECC字中的错误。控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

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