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1. 发明申请

US20070038693A1 Method and Processor for Performing a Floating-Point Instruction Within a Processor 审中-公开
标题翻译：在处理器内执行浮点指令的方法和处理器
公开(公告)号：US20070038693A1
公开(公告)日：2007-02-15
申请号：US11462069
申请日：2006-08-03
申请人： Christian Jacobi , Matthias Klein , Silvia Mueller , Matthias Pflanz , Jochen Preiss
发明人： Christian Jacobi , Matthias Klein , Silvia Mueller , Matthias Pflanz , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/49936
摘要： The invention relates to a method for performing floating-point instructions within a processor of a data processing system is described, wherein an input of said floating-point instruction comprises a normal or a denormal floating-point number. Said method comprises the steps of storing said floating-point number, normalization of said floating-point number by counting the leading zeros of the mantissa, shifting the fraction part to the left by the number of leading zeros and simultaneously decrementing the exponent by one for every position that the fraction part is shifted to the left, wherein it the input is a normal floating point number the normalization is done after counting no leading zero of the mantissa, execution of a floating point instruction, wherein said normalized floating-point number is utilized as input for the floating point instruction, and storing of a floating-point result. Furthermore a processor to be used to perform said method is described.
摘要翻译：本发明涉及一种用于在数据处理系统的处理器内执行浮点指令的方法，其中所述浮点指令的输入包括正常或非正常浮点数。所述方法包括以下步骤：存储所述浮点数，通过对尾数的前导零进行计数来归一化所述浮点数，将分数部分向左移动前导零的数量，同时将指数递减1，分数部分向左移动的每个位置，其中输入是普通浮点数，在不计算尾数的前导零之后进行归一化，执行浮点指令，其中所述标准化浮点数为用作浮点指令的输入，以及浮点结果的存储。此外，描述了用于执行所述方法的处理器。

2. 发明申请

US20060184601A1 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US20060184601A1
公开(公告)日：2006-08-17
申请号：US11055812
申请日：2005-02-11
申请人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
发明人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准移位量计算选择信号i 指出对齐逻辑（3）输出的最高有效位是否具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6 ）。

3. 发明申请

US20070050435A1 Leading-Zero Counter and Method to Count Leading Zeros 审中-公开
标题翻译：领先的零计数器和计算领先零的方法
公开(公告)号：US20070050435A1
公开(公告)日：2007-03-01
申请号：US11459663
申请日：2006-07-25
申请人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
发明人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
IPC分类号： G06F15/00
CPC分类号： G06F7/74
摘要： The present invention relates to a circuit comprising a Leading Zero Counter (LZC) sub-circuit driving a second sub-circuit, like a shifter or arbiter. Shifter circuits or arbiter circuits operating with fewer stages than before have a smaller delay since every stage can select between more than two inputs. This reduces the overall delay of the shifter, arbiter, etc. But for state-of-the art binary LZC circuits this requires a complex recoding between LZC and shifter circuit. In order to provide an improved leading zero circuit having an output which allows a simpler control of a post-connected sub-circuit having two or more stages and having at least one stage with three or more inputs, it is proposed to provide a LZC circuitry providing an output consisting of two or more unary encoded substrings. This removes the requirement for a recoder between LZC and shifter.
摘要翻译：本发明涉及一种包括驱动第二子电路的前导零计数器（LZC）子电路的电路，如移相器或仲裁器。移动器电路或仲裁器电路的运行次数比以前更少，延迟较小，因为每个阶段都可以在两个以上的输入之间进行选择。这减少了移位器，仲裁器等的总体延迟。但是对于最先进的二进制LZC电路，这需要LZC和移位器电路之间的复杂重新编码。为了提供具有输出的改进的前导零电路，其允许更简单地控制具有两个或更多个级的后连接子电路并且具有至少一个具有三个或更多个输入的级，所以建议提供一种LZC电路提供由两个或更多个一元编码的子串组成的输出。这消除了对LZC和移位器之间的重新编码器的要求。

4. 发明授权

US07461117B2 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准偏移量计算指示mo的选择信号对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。

5. 发明申请

US20120284548A1 Zero Indication Forwarding for Floating Point Unit Power Reduction 失效
标题翻译：浮点单元功率降低的零指示转发
公开(公告)号：US20120284548A1
公开(公告)日：2012-11-08
申请号：US13552327
申请日：2012-07-18
申请人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
发明人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译：一种在处理数学运算时降低功耗的方法和系统。在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。当至少一个操作数为零操作数或至少一个操作数无序时，会设置一个触发门控时钟信号的标志。时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。

6. 发明申请

US20100146023A1 SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION 有权
标题翻译：具有全功能和全零检测功能
公开(公告)号：US20100146023A1
公开(公告)日：2010-06-10
申请号：US12331702
申请日：2008-12-10
申请人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
发明人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
IPC分类号： G06F7/00
CPC分类号： G06F5/01 , G06F7/02
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译：一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端，移位器。检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作，并行地移动到由最终变速级执行的换档操作以产生转换结果。

7. 发明申请

US20100063987A1 SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR 有权
标题翻译：支持浮点处理器中的多个格式
公开(公告)号：US20100063987A1
公开(公告)日：2010-03-11
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译：在二进制浮点处理器中，通过使用结果精度（“Emin”）的最小指数值偏移指数，即将重新编码的值转换为内部格式，将各种类型的操作数中的每一个的指数重新编码为内部格式指数是指数减去Emin的表示值。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。然后以这种新格式执行指数计算。对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。

8. 发明申请

US20100057825A1 METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING 失效
标题翻译：方法和电子计算电路，用于通过饱和同步信息处理进行模块化增加的操作宽度减小
公开(公告)号：US20100057825A1
公开(公告)日：2010-03-04
申请号：US12028889
申请日：2008-02-11
申请人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
发明人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
IPC分类号： G06F7/50
CPC分类号： G06F7/727 , G06F7/499
摘要： A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.
摘要翻译：描述了一种操作数宽度减小的方法，其中处理位宽N为N的两个N位输入操作数（A，B），并减少位宽M的M位输出操作数（A'，B'）以一种方式产生，包括在所述两个M位输出操作数（A'，B'）上执行的对M位进行饱和后的M位加法器功能的后处理提供等于M的M位结果两个N位输入操作数（A，B）的N位模加法器功能的比特结果，后跟饱和至M位。进一步描述执行所述方法的电子计算电路（1,5）。另外，描述了包括这种电子计算电路的计算机系统。

9. 发明授权

US08626807B2 Reuse of rounder for fixed conversion of log instructions 有权
标题翻译：重复使用圆形固定转换日志指令
公开(公告)号：US08626807B2
公开(公告)日：2014-01-07
申请号：US12350680
申请日：2009-01-08
申请人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
发明人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
摘要翻译：一种用于将有符号固定点数转换为浮点数的方法，该浮点数包括读取与要转换的有符号固定点数相对应的输入数，确定输入数是否小于零，根据输入数量小于零或大于或等于零，通过将输入数字与符号位进行异或运算来计算第一中间结果，计算第一中间结果的前导零，基于符号位填充第一中间结果，通过将填充的第一中间结果向左移动前导零来计算第二中间结果，计算指数部分和分数部分，基于符号位有条件地增加分数部分，校正指数部分和分数部分，如果递增分数部分溢出，返回浮点数。

10. 发明授权

US08578196B2 Zero indication forwarding for floating point unit power reduction 失效
标题翻译：用于浮点单元功率降低的零指示转发
公开(公告)号：US08578196B2
公开(公告)日：2013-11-05
申请号：US13552327
申请日：2012-07-18
申请人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
发明人： Harry S. Barowski , Maarten J. Boersma , Silvia M. Mueller , Tim Niggemeier , Jochen Preiss
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译：一种在处理数学运算时降低功耗的方法和系统。在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。

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