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1. 发明申请

US20060184601A1 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US20060184601A1
公开(公告)日：2006-08-17
申请号：US11055812
申请日：2005-02-11
申请人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
发明人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准移位量计算选择信号i 指出对齐逻辑（3）输出的最高有效位是否具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6 ）。

2. 发明申请

US20070050435A1 Leading-Zero Counter and Method to Count Leading Zeros 审中-公开
标题翻译：领先的零计数器和计算领先零的方法
公开(公告)号：US20070050435A1
公开(公告)日：2007-03-01
申请号：US11459663
申请日：2006-07-25
申请人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
发明人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
IPC分类号： G06F15/00
CPC分类号： G06F7/74
摘要： The present invention relates to a circuit comprising a Leading Zero Counter (LZC) sub-circuit driving a second sub-circuit, like a shifter or arbiter. Shifter circuits or arbiter circuits operating with fewer stages than before have a smaller delay since every stage can select between more than two inputs. This reduces the overall delay of the shifter, arbiter, etc. But for state-of-the art binary LZC circuits this requires a complex recoding between LZC and shifter circuit. In order to provide an improved leading zero circuit having an output which allows a simpler control of a post-connected sub-circuit having two or more stages and having at least one stage with three or more inputs, it is proposed to provide a LZC circuitry providing an output consisting of two or more unary encoded substrings. This removes the requirement for a recoder between LZC and shifter.
摘要翻译：本发明涉及一种包括驱动第二子电路的前导零计数器（LZC）子电路的电路，如移相器或仲裁器。移动器电路或仲裁器电路的运行次数比以前更少，延迟较小，因为每个阶段都可以在两个以上的输入之间进行选择。这减少了移位器，仲裁器等的总体延迟。但是对于最先进的二进制LZC电路，这需要LZC和移位器电路之间的复杂重新编码。为了提供具有输出的改进的前导零电路，其允许更简单地控制具有两个或更多个级的后连接子电路并且具有至少一个具有三个或更多个输入的级，所以建议提供一种LZC电路提供由两个或更多个一元编码的子串组成的输出。这消除了对LZC和移位器之间的重新编码器的要求。

3. 发明申请

US20070038693A1 Method and Processor for Performing a Floating-Point Instruction Within a Processor 审中-公开
标题翻译：在处理器内执行浮点指令的方法和处理器
公开(公告)号：US20070038693A1
公开(公告)日：2007-02-15
申请号：US11462069
申请日：2006-08-03
申请人： Christian Jacobi , Matthias Klein , Silvia Mueller , Matthias Pflanz , Jochen Preiss
发明人： Christian Jacobi , Matthias Klein , Silvia Mueller , Matthias Pflanz , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/49936
摘要： The invention relates to a method for performing floating-point instructions within a processor of a data processing system is described, wherein an input of said floating-point instruction comprises a normal or a denormal floating-point number. Said method comprises the steps of storing said floating-point number, normalization of said floating-point number by counting the leading zeros of the mantissa, shifting the fraction part to the left by the number of leading zeros and simultaneously decrementing the exponent by one for every position that the fraction part is shifted to the left, wherein it the input is a normal floating point number the normalization is done after counting no leading zero of the mantissa, execution of a floating point instruction, wherein said normalized floating-point number is utilized as input for the floating point instruction, and storing of a floating-point result. Furthermore a processor to be used to perform said method is described.
摘要翻译：本发明涉及一种用于在数据处理系统的处理器内执行浮点指令的方法，其中所述浮点指令的输入包括正常或非正常浮点数。所述方法包括以下步骤：存储所述浮点数，通过对尾数的前导零进行计数来归一化所述浮点数，将分数部分向左移动前导零的数量，同时将指数递减1，分数部分向左移动的每个位置，其中输入是普通浮点数，在不计算尾数的前导零之后进行归一化，执行浮点指令，其中所述标准化浮点数为用作浮点指令的输入，以及浮点结果的存储。此外，描述了用于执行所述方法的处理器。

4. 发明申请

US20060101107A1 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US20060101107A1
公开(公告)日：2006-05-11
申请号：US10982110
申请日：2004-11-05
申请人： Sang Dhong , Harm Hofstee , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Harm Hofstee , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

5. 发明申请

US20060026223A1 Apparatus and method for reducing the latency of sum-addressed shifters 有权
标题翻译：用于减少和寻址移位器的延迟的装置和方法
公开(公告)号：US20060026223A1
公开(公告)日：2006-02-02
申请号：US10902475
申请日：2004-07-29
申请人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/00
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

6. 发明申请

US20060012399A1 Protecting one-hot logic against short-curcuits during power-on 失效
标题翻译：在上电期间保护热门逻辑免于短路
公开(公告)号：US20060012399A1
公开(公告)日：2006-01-19
申请号：US10891771
申请日：2004-07-15
申请人： Sang Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Mueller
发明人： Sang Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Mueller
IPC分类号： H03K19/094
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译：提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。

7. 发明申请

US20060101108A1 Using a leading-sign anticipator circuit for detecting sticky-bit information 审中-公开
标题翻译：使用前置标志预测电路检测粘滞位信息
公开(公告)号：US20060101108A1
公开(公告)日：2006-05-11
申请号：US10982119
申请日：2004-11-05
申请人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh , Yonetaro Totsuka
发明人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh , Yonetaro Totsuka
IPC分类号： G06F7/50
CPC分类号： G06F7/49952 , G06F7/483
摘要： A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sticky bit. However, this design has power consumption and area costs associated with it. To overcome these disadvantages, the OR trees of Leading Zero Counters (CLZs) are employed in conjunction with the Edge Vector logic of a Leading Sign Anticipator and an additional OR gate to determine the sticky bit.
摘要翻译：提供了一种方法，装置和计算机程序，以在浮点设计中更有效地生成粘性位。传统上，使用单独的ORing逻辑或OR树来将归一化移位器的棒输出压缩成至少一个粘性位。但是，该设计具有与之相关的功耗和面积成本。为了克服这些缺点，领先的零计数器（CLZ）的OR树结合领先标志预期者的边缘向量逻辑和附加的或门来确定粘滞位。

8. 发明申请

US20060101315A1 Leakage current reduction system and method 有权
标题翻译：漏电流减少系统及方法
公开(公告)号：US20060101315A1
公开(公告)日：2006-05-11
申请号：US10982111
申请日：2004-11-05
申请人： Sang Dhong , Hwa-Joon Oh , Silvia Mueller , Joel Silberman
发明人： Sang Dhong , Hwa-Joon Oh , Silvia Mueller , Joel Silberman
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/3008
摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.
摘要翻译：提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。传统上，采用额外的逻辑来减少漏电流。然而，减少漏电流而不牺牲精细的晶粒操作和速度可能是困难的。可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。此外，多路复用器并不并入时间路径，因此可以保留速度。

9. 发明申请

US20060259745A1 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US20060259745A1
公开(公告)日：2006-11-16
申请号：US11127848
申请日：2005-05-12
申请人： Sang Dhong , Gordon Fossum , Harm Hofstee , Brad Michael , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Gordon Fossum , Harm Hofstee , Brad Michael , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F9/44
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： A preferred embodiment of the present invention provides a method, computer program product, and processor design for supporting high-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, a preferred embodiment of the present invention incurs significantly less overhead than would specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：本发明的优选实施例提供了一种用于支持高精度浮点函数估计的方法，计算机程序产品和处理器设计，其分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，本发明的优选实施例显着减少开销，同时仍保持均匀的FPU等待时间，这允许更简单的控制逻辑。

10. 发明申请

US20060031272A1 Alignment shifter supporting multiple precisions 审中-公开
标题翻译：对准移位器支持多种精度
公开(公告)号：US20060031272A1
公开(公告)日：2006-02-09
申请号：US10912480
申请日：2004-08-05
申请人： Sang Dhong , Hwa-Joon Oh , Silvia Mueller
发明人： Sang Dhong , Hwa-Joon Oh , Silvia Mueller
IPC分类号： G06F7/00
CPC分类号： G06F5/012 , G06F7/485
摘要： An apparatus, a method, and a computer program are provided for fully utilizing a double precision Floating Point (FP) alignment shifter. In conventional FP adders, and other FP computational units, double precision FP alignment shifters are utilized to perform both double and single precision alignment shifts. However, when a conventional double precision FP alignment shifter is utilized for a single precision calculation, half of the available capacity of the double precision FP alignment shifter is wasted. Therefore, to better utilize the capacity of double precision FP alignment shifter, a modified alignment shifter is utilized that can perform either an alignment shift for a double precision calculation or two simultaneous (or nearly simultaneous) alignment shifts for two single precision calculations.
摘要翻译：提供了一种完全利用双精度浮点（FP）对准移位器的装置，方法和计算机程序。在传统的FP加法器和其他FP计算单元中，双精度FP对准移位器被用于执行双精度和单精度对准移位。然而，当将传统的双精度FP对准移位器用于单精度计算时，双精度FP对准移位器的可用容量的一半被浪费。因此，为了更好地利用双精度FP对准移位器的容量，使用改进的对准移位器，其可以执行用于双精度计算的对准移位或用于两个单精度计算的两个同时（或几乎同时）的对准移位。

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