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1. 发明申请

US20050030789A1 METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS 有权
标题翻译：用于操作由P型存储器单元组成的NAND阵列存储器模块的方法
公开(公告)号：US20050030789A1
公开(公告)日：2005-02-10
申请号：US10707562
申请日：2003-12-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
IPC分类号： G11C16/02 , G11C11/34 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.
摘要翻译：一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层注入，并且将衬底电压施加到多个存储单元的衬底。

2. 发明授权

US06952369B2 Method for operating a NAND-array memory module composed of P-type memory cells 有权
标题翻译：用于操作由P型存储单元组成的NAND阵列存储模块的方法
公开(公告)号：US06952369B2
公开(公告)日：2005-10-04
申请号：US10707562
申请日：2003-12-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
IPC分类号： G11C16/02 , G11C11/34 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.
摘要翻译：一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层注入，并且将衬底电压施加到多个存储单元的衬底。

3. 发明授权

US06801456B1 Method for programming, erasing and reading a flash memory cell 有权
标题翻译：编程，擦除和读取闪存单元的方法
公开(公告)号：US06801456B1
公开(公告)日：2004-10-05
申请号：US10707474
申请日：2003-12-17
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Jih-Wen Chou , Cheng-Tung Huang
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Jih-Wen Chou , Cheng-Tung Huang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0466
摘要： A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P+ poly gate formed on the ONO stack layer, a P+ doped source region disposed in the N-well at one side of the gate, and a P+ doped drain region disposed in the N-well at the other side of the gate. The method includes the steps of: applying a word line voltage VWL on the P+ poly gate, applying a source line voltage VSL on the source, wherein the source line voltage VSL is greater than the word line voltage VWL, thereby providing adequate bias to turn on the P channel thereof. A bit line voltage that is smaller than the source line voltage VSL is applied on the P+ doped drain region, thereby driving channel hot holes to flow toward the P+ doped drain region and then inducing hot electron injection near the drain side. A well voltage VNW is applied to the N-well, wherein VNW=VSL.
摘要翻译：公开了一种通过通道热载流子诱发的热电子注入机制来编程PMOS单晶体管闪存单元的方法。 PMOS单晶体管闪存单元包括位于半导体衬底的N阱上的ONO堆叠层，形成在ONO堆叠层上的P +多晶硅栅极，设置在N + 并且在栅极的另一侧设置在N阱中的P +掺杂漏极区。该方法包括以下步骤：在P ++多栅极上施加字线电压VWL，在源极上施加源极线电压VSL，其中源极线电压VSL大于字线电压VWL，从而提供足够的偏置以打开其P通道。小于源极线电压VSL的位线电压施加在P +掺杂漏极区域上，从而驱动通道热孔流向P +掺杂漏极区域，然后在漏极附近引入热电子注入侧。将井电压VNW施加到N阱，其中VNW = VSL。

4. 发明授权

US06617637B1 Electrically erasable programmable logic device 失效
标题翻译：电可擦除可编程逻辑器件
公开(公告)号：US06617637B1
公开(公告)日：2003-09-09
申请号：US10065718
申请日：2002-11-13
申请人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C2216/10 , H01L29/42324 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。在P型半导体衬底上形成N型阱。在N阱上形成第一PMOS晶体管。第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

5. 发明授权

US06920067B2 Integrated circuit embedded with single-poly non-volatile memory 有权
标题翻译：集成电路嵌入单聚合非易失性存储器
公开(公告)号：US06920067B2
公开(公告)日：2005-07-19
申请号：US10248193
申请日：2002-12-25
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/118
摘要： A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.
摘要翻译：芯片上系统（SOC）包含一个内核电路和一个嵌入单个多可擦除可编程只读存储器单元的阵列的输入/输出（I / O）电路，每个存储单元包括串联连接到第二个 PMOS晶体管。第一和第二PMOS晶体管都形成在P型衬底的N阱上。第一PMOS晶体管包括单多晶硅浮置栅极，第一P + SUP掺杂漏极区域和第一P + +掺杂源极区域，第二PMOS晶体管包括：多选择栅极和第二P + +掺杂源极区域，并且第一PMOS晶体管的第一P + +掺杂源极区域用作第二PMOS晶体管的漏极。

6. 发明授权

US06740556B1 Method for forming EPROM with low leakage 有权
标题翻译：低泄漏形成EPROM的方法
公开(公告)号：US06740556B1
公开(公告)日：2004-05-25
申请号：US10249075
申请日：2003-03-14
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.
摘要翻译：一种用于形成电可编程只读存储器（EPROM）的方法包括在N阱上形成第一p +掺杂区，第二p +掺杂区和第三p +掺杂区，形成在第一p +掺杂区和第二p +掺杂区之间的控制栅极，以及在第二p +掺杂区和第三p +掺杂区之间形成p + +浮置栅。

7. 发明授权

US06710397B1 Nonvolatile semiconductor memory device having divided bit lines 失效
标题翻译：具有划分位线的非易失性半导体存储器件
公开(公告)号：US06710397B1
公开(公告)日：2004-03-23
申请号：US10604406
申请日：2003-07-17
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L29788
CPC分类号： G11C16/24
摘要： A non-volatile semiconuctor memory device having divided bit lines. A main bit line controlled by at least one bit line selection device to transfer its potential selected sub bit line, such that memory cells in a selected work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.
摘要翻译：具有划分位线的非易失性半导体存储器件。由至少一个位线选择装置控制的主位线传送其潜在的选择的子位线，使得可以防止所选择的工作中的存储器单元和由寄生电容产生的位线的过载。存储单元和位线选择装置分别并排布置在P阱和N阱中，从而防止在编程或擦除位线期间的干扰。

8. 发明授权

US06678190B2 Single poly embedded eprom 有权
标题翻译：单聚嵌入eprom
公开(公告)号：US06678190B2
公开(公告)日：2004-01-13
申请号：US10055047
申请日：2002-01-25
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0433 , G11C2216/10 , H01L27/11558
摘要： An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode.
摘要翻译：一种可擦除可编程只读存储器，包括两个串联连接的P型金属氧化物半导体（MOS）晶体管，其中在布局结构中省略了控制栅极，因为在编程模式期间偏置不需要应用于浮动栅极。

9. 发明授权

US06677198B2 Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof 失效
标题翻译：低电压通道写入/擦除闪存单元的结构及其制造方法
公开(公告)号：US06677198B2
公开(公告)日：2004-01-13
申请号：US10064109
申请日：2002-06-12
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7883
摘要： The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. The present invention can apply the same voltage to the deep P-well and the N-well on the N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.
摘要翻译：本发明涉及一种低电压通道写入/擦除闪速存储单元的结构及其制造方法，该结构包括N衬底，在衬底上形成的深P阱以及形成在N阱上的N阱深P井。将深P型区域和浅P型区域离子注入到N阱中。深P型区域连接到浅P型区域。在深p型区域中离子注入n型区域，与深p型区域电短路并用作漏极。另一个n型区域也被离子注入在用作源的浅P型区域的一侧。本发明可以通过添加三阱结构将相同的电压施加在N衬底上的深P阱和N阱上，使得可以产生的泄漏电流可以减小到最小，从而有效地减少最终电压，当执行擦除操作，简化了整个结构所需的电荷泵电路的设计复杂度，提高了运行效率。

10. 发明授权

US06489202B1 Structure of an embedded channel write-erase flash memory cell and fabricating method thereof 失效
标题翻译：嵌入式通道写入 - 擦除闪存单元的结构及其制造方法
公开(公告)号：US06489202B1
公开(公告)日：2002-12-03
申请号：US09865432
申请日：2001-05-29
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultaneously fabricated on a substrate to reduce the cost and to simplify the process flow. Moreover, CMOS devices capable of performing high-voltage and low-voltage operations are reserved. Therefore, the present invention can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.
摘要翻译：本发明涉及嵌入式通道写入/擦除闪存单元的结构及其制造方法，更具体地说，涉及组合CMOS器件和闪存单元的结构，其中闪存单元结构和CMOS器件同时制造在一种降低成本并简化工艺流程的基板。此外，保留能够执行高电压和低电压操作的CMOS器件。因此，本发明不仅可以有效提高闪存单元和CMOS器件的工作效率，而且其整体体积也小于通过组合分别设计和制造的CMOS器件和闪存单元获得的整体体积。

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