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1. 发明授权

US06617637B1 Electrically erasable programmable logic device 失效
标题翻译：电可擦除可编程逻辑器件
公开(公告)号：US06617637B1
公开(公告)日：2003-09-09
申请号：US10065718
申请日：2002-11-13
申请人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C2216/10 , H01L29/42324 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。在P型半导体衬底上形成N型阱。在N阱上形成第一PMOS晶体管。第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

2. 发明授权

US06829166B2 Method for controlling a non-volatile dynamic random access memory 有权
标题翻译：用于控制非易失性动态随机存取存储器的方法
公开(公告)号：US06829166B2
公开(公告)日：2004-12-07
申请号：US10065042
申请日：2002-09-13
申请人： Yen-Tai Lin , Shih-Jye Shen
发明人： Yen-Tai Lin , Shih-Jye Shen
IPC分类号： G11C1604
CPC分类号： G11C14/00
摘要： A method for controlling a non-volatile dynamic random access memory provides a non-volatile dynamic random access memory having a storage unit and a control unit. The storage unit has a floating gate for storing charges and a control gate for receiving an operating voltage to determine whether a channel is induced on the surface of a substrate. The channel corresponds to a number of charges stored on the floating gate. A parasitic capacitor exists between the storage unit and the control unit, and a capacitance of the parasitic capacitor increases when the channel has been induced. The method includes applying a first predetermined voltage to the control unit and measuring a voltage variance generated by the parasitic capacitor to analyze data stored by the storage unit.
摘要翻译：用于控制非易失性动态随机存取存储器的方法提供具有存储单元和控制单元的非易失性动态随机存取存储器。存储单元具有用于存储电荷的浮动栅极和用于接收工作电压的控制栅极，以确定在衬底的表面上是否感应通道。信道对应于存储在浮动门上的多个电荷。在存储单元和控制单元之间存在寄生电容器，并且当感应通道时，寄生电容器的电容增加。该方法包括向控制单元施加第一预定电压并测量由寄生电容器产生的电压变化，以分析由存储单元存储的数据。

3. 发明申请

US20130064027A1 Memory and Method of Adjusting Operating Voltage thereof 审中-公开
标题翻译：记忆和调整其工作电压的方法
公开(公告)号：US20130064027A1
公开(公告)日：2013-03-14
申请号：US13231980
申请日：2011-09-14
申请人： Meng-Yi Wu , Wein-Town Sun , Yen-Tai Lin , Cheng-Jye Liu , Chiun-Chi Shen
发明人： Meng-Yi Wu , Wein-Town Sun , Yen-Tai Lin , Cheng-Jye Liu , Chiun-Chi Shen
IPC分类号： G11C29/00
CPC分类号： G11C29/021 , G11C11/40 , G11C29/028 , G11C29/50016 , G11C2029/5002
摘要： By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.
摘要翻译：通过根据指示存储单元的未测试电容器的电容的测量电容结果来调节存储器中的存储单元的工作电压，可以总是根据所测量的电容结果确定存储单元的适当工作电压。测量的电容结果表示指示存储单元的栅极电介质的特性的未测试电容器的电容是否高于或低于参考电容器，并且通过放大表示参考电容器的电容的两个电压之间的差来产生和被测电容器的电容。

4. 发明申请

US20070159883A1 Method and Related Apparatus Capable of Improving Endurance of Memory 审中-公开
标题翻译：能够提高记忆力的方法和相关装置
公开(公告)号：US20070159883A1
公开(公告)日：2007-07-12
申请号：US11531278
申请日：2006-09-13
申请人： Ching-Yuan Lin , Yen-Tai Lin
发明人： Ching-Yuan Lin , Yen-Tai Lin
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/349 , G11C16/102 , G11C16/3495
摘要： A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells, if the record cell is the last non-programmed record cell of the set of record cells that includes the record cell. The method further includes programming the record cell corresponding to a first non-programmed record cell in the set of record cells if the non-programmed record cell is not the last non-programmed record cell of the set of record cells.
摘要翻译：能够提高存储器耐久性的方法包括检测记录单元是否是包括记录单元的一组记录单元的最后一个非编程记录单元。如果记录单元是包括记录单元的记录单元组的最后一个未编程的记录单元，则该方法包括擦除相应的多次可编程存储器块组并擦除记录单元组。该方法还包括如果非编程记录单元不是该组记录单元的最后一个非编程记录单元，则编程对应于记录单元组中的第一非编程记录单元的记录单元。

5. 发明授权

US08373485B2 Voltage level shifting apparatus 有权
标题翻译：电压电平转换装置
公开(公告)号：US08373485B2
公开(公告)日：2013-02-12
申请号：US13090283
申请日：2011-04-20
申请人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
发明人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.
摘要翻译：公开了一种电压电平转换装置。电压电平移位装置具有交叉耦合晶体管对，多个晶体管对，第一二极管串，第二二极管串和输入晶体管对。晶体管对中的一个耦合到交叉耦合晶体管对，并且晶体管对由多个参考电压控制。第一和第二二极管串耦合在两个晶体管对之间。第一和第二二极管串中的每一个具有至少一个二极管。输入晶体管对接收第一和第二输入电压，第一和第二输入电压是互补信号。交叉耦合晶体管对通过移位第一和第二输入电压的电压电平来产生并输出第一输出电压和第二输出电压。

6. 发明申请

US20080165587A1 OPERATING METHOD OF P-CHANNEL NON-VOLATILE MEMORY 失效
标题翻译： P-CHANNEL非易失性存储器的操作方法
公开(公告)号：US20080165587A1
公开(公告)日：2008-07-10
申请号：US12046477
申请日：2008-03-12
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C11/34
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.
摘要翻译：描述P沟道非易失性存储器。 P沟道非易失性存储器包括衬底，第一存储单元和第二存储单元。在衬底上设置N阱，并且将第一电池和第二电池设置在N阱上。第一存储单元包括第一栅极，第一电荷存储结构，第一掺杂区和第二掺杂区。第一掺杂区域和第二掺杂区域设置在第一栅极的相应侧面上的衬底中。第二单元包括第二栅极，第二电荷存储结构，第三掺杂区和第二掺杂区。第三掺杂区域和第二掺杂区域设置在第二栅极的相应侧上的衬底中。第二单元和第一单元共享第二掺杂区。

7. 发明申请

US20080159008A1 OPERATING METHOD OF P-CHANNEL NON-VOLATILE MEMORY 审中-公开
公开(公告)号：US20080159008A1
公开(公告)日：2008-07-03
申请号：US12045030
申请日：2008-03-10
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C11/34
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.

8. 发明申请

US20060262626A1 METHOD FOR ACCESSING MEMORY 有权
标题翻译：访问存储器的方法
公开(公告)号：US20060262626A1
公开(公告)日：2006-11-23
申请号：US11163431
申请日：2005-10-19
申请人： Ching-Yuan Lin , Hong-Yi Liao , Yen-Tai Lin , Shih-Yun Lin , Chun-Hung Lu
发明人： Ching-Yuan Lin , Hong-Yi Liao , Yen-Tai Lin , Shih-Yun Lin , Chun-Hung Lu
IPC分类号： G11C17/18
CPC分类号： G11C16/105 , G11C16/3495 , G11C17/146 , G11C17/18 , G11C2216/26
摘要： The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.
摘要翻译：本发明提供一种访问存储器的方法。存储器包含M个一次性可编程存储器块，并且每个具有第一存储器扇区和第二存储器扇区。该方法包括：选择第一目标存储块并读取第一目标存储块。通过按照搜索规则比较来自M个一次可编程存储器块的N个一次可编程存储器块的第二存储器扇区来选择第一目标存储器块来选择第一目标存储器块的步骤来选择第一目标存储器块。

9. 发明授权

US6153463A Triple plate capacitor and method for manufacturing 有权
标题翻译：三板式电容器及其制造方法
公开(公告)号：US6153463A
公开(公告)日：2000-11-28
申请号：US350478
申请日：1999-07-09
申请人： Hon-Sco Wei , Yen-Tai Lin
发明人： Hon-Sco Wei , Yen-Tai Lin
IPC分类号： H01L21/02 , H01L29/94 , H01L21/8242
CPC分类号： H01L28/40 , H01L29/94
摘要： A novel capacitor design and construction method that uses a stacked structure which is sometimes otherwise used for a so-called floating gate transistor. A first electrical contact is electrically coupled with a conductive region formed in the substrate and with a control gate layer. A second electrical contact is electrically coupled with a floating gate layer, forming a plate between the substrate and control gate layers. The footprint of this capacitor is reduced by using both sides of the floating gate layer as capacitive plate. Parasitic capacitance is relatively reduced. One or more dielectric layers can be formed for both capacitors and for floating gate transistors on the substrate in the same process step or steps.
摘要翻译：一种新颖的电容器设计和施工方法，其使用有时另外用于所谓的浮栅晶体管的堆叠结构。第一电触头与形成在基板中的导电区域和控制栅极层电耦合。第二电接触件与浮栅层电耦合，在衬底和控制栅极层之间形成一个板。通过使用浮动栅极层的两侧作为电容板来减小该电容器的占位面积。寄生电容相对减小。可以在相同的工艺步骤中为两个电容器和衬底上的浮栅晶体管形成一个或多个电介质层。

10. 发明授权

US07453312B2 Voltage regulator outputting positive and negative voltages with the same offsets 有权
公开(公告)号：US07453312B2
公开(公告)日：2008-11-18
申请号：US12116229
申请日：2008-05-07
申请人： Yen-Tai Lin , Ching-Yuan Lin
发明人： Yen-Tai Lin , Ching-Yuan Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/009 , H02M2003/071
摘要： A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

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