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1. 发明申请

US20050030789A1 METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS 有权
标题翻译：用于操作由P型存储器单元组成的NAND阵列存储器模块的方法
公开(公告)号：US20050030789A1
公开(公告)日：2005-02-10
申请号：US10707562
申请日：2003-12-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
IPC分类号： G11C16/02 , G11C11/34 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.
摘要翻译：一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层注入，并且将衬底电压施加到多个存储单元的衬底。

2. 发明授权

US06801456B1 Method for programming, erasing and reading a flash memory cell 有权
标题翻译：编程，擦除和读取闪存单元的方法
公开(公告)号：US06801456B1
公开(公告)日：2004-10-05
申请号：US10707474
申请日：2003-12-17
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Jih-Wen Chou , Cheng-Tung Huang
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Jih-Wen Chou , Cheng-Tung Huang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0466
摘要： A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P+ poly gate formed on the ONO stack layer, a P+ doped source region disposed in the N-well at one side of the gate, and a P+ doped drain region disposed in the N-well at the other side of the gate. The method includes the steps of: applying a word line voltage VWL on the P+ poly gate, applying a source line voltage VSL on the source, wherein the source line voltage VSL is greater than the word line voltage VWL, thereby providing adequate bias to turn on the P channel thereof. A bit line voltage that is smaller than the source line voltage VSL is applied on the P+ doped drain region, thereby driving channel hot holes to flow toward the P+ doped drain region and then inducing hot electron injection near the drain side. A well voltage VNW is applied to the N-well, wherein VNW=VSL.
摘要翻译：公开了一种通过通道热载流子诱发的热电子注入机制来编程PMOS单晶体管闪存单元的方法。 PMOS单晶体管闪存单元包括位于半导体衬底的N阱上的ONO堆叠层，形成在ONO堆叠层上的P +多晶硅栅极，设置在N + 并且在栅极的另一侧设置在N阱中的P +掺杂漏极区。该方法包括以下步骤：在P ++多栅极上施加字线电压VWL，在源极上施加源极线电压VSL，其中源极线电压VSL大于字线电压VWL，从而提供足够的偏置以打开其P通道。小于源极线电压VSL的位线电压施加在P +掺杂漏极区域上，从而驱动通道热孔流向P +掺杂漏极区域，然后在漏极附近引入热电子注入侧。将井电压VNW施加到N阱，其中VNW = VSL。

3. 发明授权

US06952369B2 Method for operating a NAND-array memory module composed of P-type memory cells 有权
标题翻译：用于操作由P型存储单元组成的NAND阵列存储模块的方法
公开(公告)号：US06952369B2
公开(公告)日：2005-10-04
申请号：US10707562
申请日：2003-12-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Jih-Wen Chou , Cheng-Tung Huang , Chih-Hsun Chu
IPC分类号： G11C16/02 , G11C11/34 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.
摘要翻译：一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层注入，并且将衬底电压施加到多个存储单元的衬底。

4. 发明授权

US06920067B2 Integrated circuit embedded with single-poly non-volatile memory 有权
标题翻译：集成电路嵌入单聚合非易失性存储器
公开(公告)号：US06920067B2
公开(公告)日：2005-07-19
申请号：US10248193
申请日：2002-12-25
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/118
摘要： A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.
摘要翻译：芯片上系统（SOC）包含一个内核电路和一个嵌入单个多可擦除可编程只读存储器单元的阵列的输入/输出（I / O）电路，每个存储单元包括串联连接到第二个 PMOS晶体管。第一和第二PMOS晶体管都形成在P型衬底的N阱上。第一PMOS晶体管包括单多晶硅浮置栅极，第一P + SUP掺杂漏极区域和第一P + +掺杂源极区域，第二PMOS晶体管包括：多选择栅极和第二P + +掺杂源极区域，并且第一PMOS晶体管的第一P + +掺杂源极区域用作第二PMOS晶体管的漏极。

5. 发明授权

US06740556B1 Method for forming EPROM with low leakage 有权
标题翻译：低泄漏形成EPROM的方法
公开(公告)号：US06740556B1
公开(公告)日：2004-05-25
申请号：US10249075
申请日：2003-03-14
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.
摘要翻译：一种用于形成电可编程只读存储器（EPROM）的方法包括在N阱上形成第一p +掺杂区，第二p +掺杂区和第三p +掺杂区，形成在第一p +掺杂区和第二p +掺杂区之间的控制栅极，以及在第二p +掺杂区和第三p +掺杂区之间形成p + +浮置栅。

6. 发明授权

US06617637B1 Electrically erasable programmable logic device 失效
标题翻译：电可擦除可编程逻辑器件
公开(公告)号：US06617637B1
公开(公告)日：2003-09-09
申请号：US10065718
申请日：2002-11-13
申请人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C2216/10 , H01L29/42324 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。在P型半导体衬底上形成N型阱。在N阱上形成第一PMOS晶体管。第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

7. 发明授权

US08646152B2 Transversely movable hinge and folding device utilizing the same 有权
标题翻译：横向活动铰链和折叠装置
公开(公告)号：US08646152B2
公开(公告)日：2014-02-11
申请号：US13110233
申请日：2011-05-18
申请人： Zheng-Cheng Lin , Ching-Hsiang Hsu
发明人： Zheng-Cheng Lin , Ching-Hsiang Hsu
IPC分类号： E05D11/10
CPC分类号： E05F1/1207 , E05D3/04 , E05Y2201/638 , E05Y2900/606 , F16H25/186
摘要： A transversely movable hinge is mounted between a base and a cover of a folding device and has a moving assembly. The moving assembly is connected to an expansion device via a linking rod. Therefore, when the folding device is opened, the expansion device is driven to extend and is convenient for users. When the folding device is closed, the expansion device is driven to retract for saving space.
摘要翻译：横向可移动的铰链安装在折叠装置的底座和盖子之间并具有移动组件。移动组件通过连接杆连接到膨胀装置。因此，当折叠装置打开时，扩展装置被驱动延伸并且方便用户。当折叠装置关闭时，扩展装置被驱动缩回以节省空间。

8. 发明申请

US20120292201A1 Stripping Gold Components and the Method of Stripping Gold 有权
标题翻译：剥离金成分和淘金方法
公开(公告)号：US20120292201A1
公开(公告)日：2012-11-22
申请号：US13457970
申请日：2012-04-27
申请人： Ching-Hsiang Hsu
发明人： Ching-Hsiang Hsu
IPC分类号： C09K13/00 , C09K13/02 , C25F5/00 , C09K13/10
CPC分类号： C25F5/00 , C22B11/042 , C25F3/02 , C25F3/22 , Y02P10/214 , Y02W30/54
摘要： The invention provides a stripping gold component which could remove gold from substrate, comprising: a stripping gold chemical compound; and a assistant conductive compound wherein said stripping gold chemical compound bonds with gold to form covalent bond to strip gold from said substrate, said assistant conductive chemical compound helps the electric conduction and decreases the voltage, said substrate would not be damaged after stripping gold from said substrate, and the stripping gold component is cyanide free.
摘要翻译：本发明提供了一种剥离金成分，其可从基底上除去金，其包括：剥离金化合物; 和辅助导电化合物，其中所述剥离金化合物与金键合以形成共价键以从所述基底剥离金，所述辅助导电化合物有助于导电并降低电压，所述基底在从所述基底剥离金后不会被损坏底物，剥离金成分不含氰化物。

9. 发明申请

US20110057243A1 NON-VOLATILE MEMORY WITH A STABLE THRESHOLD VOLTAGE ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上具有稳定阈值电压的非易失性存储器
公开(公告)号：US20110057243A1
公开(公告)日：2011-03-10
申请号：US12943945
申请日：2010-11-11
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L27/12
CPC分类号： H01L27/115
摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.
摘要翻译：设置在SOI衬底中的非易失性存储器。非易失性存储器包括存储单元和第一导电类型掺杂区域。存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。栅极设置在SOI衬底上。电荷存储结构设置在栅极和SOI衬底之间。底部电介质层设置在电荷存储层和SOI衬底之间。第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

10. 发明授权

US07655782B2 Modified mite allergen and pharmaceutical uses thereof 有权
标题翻译：改性螨过敏原及其制药用途
公开(公告)号：US07655782B2
公开(公告)日：2010-02-02
申请号：US11778934
申请日：2007-07-17
申请人： Ching-Hsiang Hsu , Wei-Chih Su
发明人： Ching-Hsiang Hsu , Wei-Chih Su
IPC分类号： C07H21/02 , C07H21/04
CPC分类号： A61K39/35 , C07H21/04 , C07K14/43531 , Y10S530/868
摘要： The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.
摘要翻译：本发明提供了当暴露于抗原时具有抑制IgE结合的能力的修饰的Dermatophagoides pteronyssinus变应原Der p 5蛋白。还提供了治疗过敏的方法，其包括将治疗有效剂量的经修饰的D.tteronyssinus变应原Der p 5蛋白施用于患有过敏Der p 5的受试者。

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