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1. 发明授权

US06617637B1 Electrically erasable programmable logic device 失效
标题翻译：电可擦除可编程逻辑器件
公开(公告)号：US06617637B1
公开(公告)日：2003-09-09
申请号：US10065718
申请日：2002-11-13
申请人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C2216/10 , H01L29/42324 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。在P型半导体衬底上形成N型阱。在N阱上形成第一PMOS晶体管。第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

2. 发明授权

US06920067B2 Integrated circuit embedded with single-poly non-volatile memory 有权
标题翻译：集成电路嵌入单聚合非易失性存储器
公开(公告)号：US06920067B2
公开(公告)日：2005-07-19
申请号：US10248193
申请日：2002-12-25
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/118
摘要： A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.
摘要翻译：芯片上系统（SOC）包含一个内核电路和一个嵌入单个多可擦除可编程只读存储器单元的阵列的输入/输出（I / O）电路，每个存储单元包括串联连接到第二个 PMOS晶体管。第一和第二PMOS晶体管都形成在P型衬底的N阱上。第一PMOS晶体管包括单多晶硅浮置栅极，第一P + SUP掺杂漏极区域和第一P + +掺杂源极区域，第二PMOS晶体管包括：多选择栅极和第二P + +掺杂源极区域，并且第一PMOS晶体管的第一P + +掺杂源极区域用作第二PMOS晶体管的漏极。

3. 发明授权

US06740556B1 Method for forming EPROM with low leakage 有权
标题翻译：低泄漏形成EPROM的方法
公开(公告)号：US06740556B1
公开(公告)日：2004-05-25
申请号：US10249075
申请日：2003-03-14
申请人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Chih-Hsun Chu , Ming-Chou Ho , Shih-Jye Shen
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.
摘要翻译：一种用于形成电可编程只读存储器（EPROM）的方法包括在N阱上形成第一p +掺杂区，第二p +掺杂区和第三p +掺杂区，形成在第一p +掺杂区和第二p +掺杂区之间的控制栅极，以及在第二p +掺杂区和第三p +掺杂区之间形成p + +浮置栅。

4. 发明申请

US20070111357A1 MANUFACTURING METHOD OF A NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的制造方法
公开(公告)号：US20070111357A1
公开(公告)日：2007-05-17
申请号：US11557111
申请日：2006-11-07
申请人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L21/00
CPC分类号： G11C16/0475 , G11C16/0425 , G11C16/0466 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.
摘要翻译：提供了形成在第一导电型基板上的非易失性存储器。非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。栅极形成在第一导电类型的基板上。第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。第二面与第一面相反。

5. 发明申请

US20070108507A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20070108507A1
公开(公告)日：2007-05-17
申请号：US11557974
申请日：2006-11-09
申请人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/788
CPC分类号： G11C16/0475 , G11C16/0425 , G11C16/0466 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.
摘要翻译：提供了形成在第一导电型基板上的非易失性存储器。非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。栅极形成在第一导电类型的基板上。第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。第二面与第一面相反。

6. 发明授权

US06914825B2 Semiconductor memory device having improved data retention 有权
标题翻译：具有改进的数据保持的半导体存储器件
公开(公告)号：US06914825B2
公开(公告)日：2005-07-05
申请号：US10249366
申请日：2003-04-03
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Ming-Chou Ho
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A NVM device encompasses a MOS select transistor including a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region. A MOS floating gate transistor is serially electrically connected to the MOS select transistor. The MOS floating gate transistor comprises a floating gate, a second source doping region electrically connected to the first drain doping region of the MOS select transistor, and a second drain doping region electrically connected to a bit line. The second source doping region and the second drain doping region define a floating gate channel. When the MOS floating gate transistor is programmed via a hot electron injection (HEI) mode, the floating gate is a P+ doped floating gate; when the MOS floating gate transistor is programmed via a hot hole injection (HHI) mode, the floating gate is an N+ doped floating gate.
摘要翻译： NVM器件包括MOS选择晶体管，其包括电连接到字线的选择栅极，电连接到源极线的第一源极掺杂区域和第一漏极掺杂区域。 MOS浮栅晶体管与MOS选择晶体管串联电连接。 MOS浮栅晶体管包括浮置栅极，电连接到MOS选择晶体管的第一漏极掺杂区域的第二源极掺杂区域和电连接到位线的第二漏极掺杂区域。第二源极掺杂区域和第二漏极掺杂区域限定浮动栅极沟道。当通过热电子注入（HEI）模式对MOS浮栅晶体管进行编程时，浮栅是P + 当通过热空穴注入（HHI）模式来编程MOS浮栅晶体管时，浮置栅极是掺杂N +的浮栅。

7. 发明授权

US06842374B2 Method for operating N-channel electrically erasable programmable logic device 有权
标题翻译：用于操作N沟道电可擦除可编程逻辑器件的方法
公开(公告)号：US06842374B2
公开(公告)日：2005-01-11
申请号：US10248283
申请日：2003-01-06
申请人： Kung-Hong Lee , Ching-Hsiang Hsu , Ya-Chin King , Shih-Jye Shen , Ming-Chou Ho
发明人： Kung-Hong Lee , Ching-Hsiang Hsu , Ya-Chin King , Shih-Jye Shen , Ming-Chou Ho
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11558 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate. By Applying a sufficient voltage on the first N-type doped region (VBL), and changing a select gate voltage (VSG) or the third N-type doped region voltage (VSL) applied on the second gate of the EEPLD, the operation of the EEPLD can be selectively implemented either under a channel hot hole (CHH) program mode or a channel hot electron (CHE) erase mode.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包含P型衬底。第一N型掺杂区域设置在P型衬底中。用于存储数据的第一栅极覆盖P型衬底并与第一N型掺杂区域相邻。第二N型掺杂区域横向设置在P型衬底中。第二N型掺杂区域也与第一栅极相邻。作为EEPLD的选择栅极或选择栅极的第二栅极覆盖P型衬底并与第二N型掺杂区域相邻。在P型衬底中设置第三N型掺杂区域。第三N型掺杂区域与第二栅极相邻。通过在第一N型掺杂区域（VBL）上施加足够的电压，并且改变施加在EEPLD的第二栅极上的选择栅极电压（VSG）或第三N型掺杂区域电压（VSL），操作可以在通道热孔（CHH）编程模式或通道热电子（CHE）擦除模式）下选择性地实施EEPLD。

8. 发明申请

US20080138956A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20080138956A1
公开(公告)日：2008-06-12
申请号：US11962126
申请日：2007-12-21
申请人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L21/336
CPC分类号： G11C16/0475 , G11C16/0425 , G11C16/0466 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.
摘要翻译：提供了形成在第一导电类型基板上的半导体器件。该器件包括栅极，第二导电型漏极区域，第二导电型源极区域和第二导电型第一轻掺杂区域。栅极形成在第一导电类型的基板上。第二导电型漏极区域和第二导电型源极区域形成在栅极两侧的第一导电型衬底中。第二导电类型的第一轻掺杂区域形成在栅极和第二导电型源极区域之间的第一导电型衬底中。

9. 发明申请

US20070109869A1 OPERATION METHOD OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的操作方法
公开(公告)号：US20070109869A1
公开(公告)日：2007-05-17
申请号：US11557975
申请日：2006-11-09
申请人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0425 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.
摘要翻译：提供了形成在第一导电型基板上的非易失性存储器。非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。栅极形成在第一导电类型的基板上。第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。第二面与第一面相反。

10. 发明申请

US20070108470A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070108470A1
公开(公告)日：2007-05-17
申请号：US11557112
申请日：2006-11-07
申请人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L31/00
CPC分类号： G11C16/0475 , G11C16/0425 , G11C16/0466 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.
摘要翻译：提供了形成在第一导电类型基板上的半导体器件。该器件包括栅极，第二导电型漏极区域，第二导电型源极区域和第二导电型第一轻掺杂区域。栅极形成在第一导电类型的基板上。第二导电型漏极区域和第二导电型源极区域形成在栅极两侧的第一导电型衬底中。第二导电类型的第一轻掺杂区域形成在栅极和第二导电型源极区域之间的第一导电型衬底中。

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