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1. 发明授权

US07649233B2 High performance transistor with a highly stressed channel 有权
标题翻译：具有高应力通道的高性能晶体管
公开(公告)号：US07649233B2
公开(公告)日：2010-01-19
申请号：US11950467
申请日：2007-12-05
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

2. 发明授权

US07253481B2 High performance MOS device with graded silicide 有权
标题翻译：具有分级硅化物的高性能MOS器件
公开(公告)号：US07253481B2
公开(公告)日：2007-08-07
申请号：US11181521
申请日：2005-07-14
申请人： Chih-Hao Wang , Ta-Wei Wang , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Ching-Wei Tsai
IPC分类号： H01L29/772
CPC分类号： H01L29/7843 , H01L29/41766 , H01L29/456 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.
摘要翻译：提供了具有较少的电流拥挤效应的半导体器件及其形成方法。半导体器件包括衬底，衬底上的栅极，沿着栅极的边缘并覆盖衬底的一部分的栅极间隔区，衬底中的扩散区域，其中扩散区域包括第一部分和第二部分之间第一部分和栅极间隔物。扩散区域的第一部分具有凹入的顶表面。半导体器件还包括在扩散区上的硅化物层，以及至少在硅化物层上的覆盖层。盖层向半导体器件的沟道区域提供应变。

3. 发明申请

US20060163672A1 High performance CMOS device design 有权
公开(公告)号：US20060163672A1
公开(公告)日：2006-07-27
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

4. 发明授权

US07323392B2 High performance transistor with a highly stressed channel 有权
标题翻译：具有高应力通道的高性能晶体管
公开(公告)号：US07323392B2
公开(公告)日：2008-01-29
申请号：US11391061
申请日：2006-03-28
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

5. 发明申请

US20070231999A1 High performance transistor with a highly stressed channel 有权
标题翻译：具有高应力通道的高性能晶体管
公开(公告)号：US20070231999A1
公开(公告)日：2007-10-04
申请号：US11391061
申请日：2006-03-28
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

6. 发明申请

US20070013010A1 High performance MOS device with graded silicide 有权
公开(公告)号：US20070013010A1
公开(公告)日：2007-01-18
申请号：US11181521
申请日：2005-07-14
申请人： Chih-Hao Wang , Ta-Wei Wang , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Ching-Wei Tsai
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L29/41766 , H01L29/456 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.

7. 发明授权

US08507951B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US08507951B2
公开(公告)日：2013-08-13
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

8. 发明授权

US07564108B2 Nitrogen treatment to improve high-k gate dielectrics 有权
标题翻译：氮处理改善高k栅极电介质
公开(公告)号：US07564108B2
公开(公告)日：2009-07-21
申请号：US11115932
申请日：2005-04-27
申请人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/76829 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.
摘要翻译：公开了具有氮化栅极电介质的MOSFET及其制造。该方法包括提供衬底并在衬底上沉积非高k电介质材料。非高k电介质包括两层。与衬底相邻的第一层基本上是无氮的，第二层包括约1015个原子/ cm3到约1022个原子/ cm3的氮。 MOSFET还包括在氮化的非高k电介质上的高k电介质材料。高k电介质优选包括HfSiON，ZrSiON或氮化Al 2 O 3。实施例还包括其中核心和外围集成电路区域被分开优化的不对称制造技术。

9. 发明申请

US20080087892A1 High Performance Transistor with a Highly Stressed Channel 有权
标题翻译：具有高度通道的高性能晶体管
公开(公告)号：US20080087892A1
公开(公告)日：2008-04-17
申请号：US11950467
申请日：2007-12-05
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L29/778 , H01L29/04
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

10. 发明授权

US07465972B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US07465972B2
公开(公告)日：2008-12-16
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L31/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

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