专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07592619B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07592619B2
公开(公告)日：2009-09-22
申请号：US11622490
申请日：2007-01-12
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： H01L29/15
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

2. 发明申请

US20080132019A1 Short channel effect engineering in MOS device using epitaxially carbon-doped silicon 有权
标题翻译：使用外延碳掺杂硅的MOS器件中的短沟道效应工程
公开(公告)号：US20080132019A1
公开(公告)日：2008-06-05
申请号：US11633721
申请日：2006-12-05
申请人： Keh-Chiang Ku , Pang-Yen Tsai , Chun-Feng Nieh , Li-Ting Wang
发明人： Keh-Chiang Ku , Pang-Yen Tsai , Chun-Feng Nieh , Li-Ting Wang
IPC分类号： H01L21/04
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.
摘要翻译：一种用于形成半导体结构的方法包括提供半导体衬底，在半导体衬底上形成栅极堆叠，以及外围生长与栅堆叠相邻的轻掺杂源极/漏极（LDD）区域，其中碳同时掺杂到LDD区域。

3. 发明申请

US20070148919A1 Multi-step epitaxial process for depositing Si/SiGe 有权
标题翻译：用于沉积Si / SiGe的多步外延工艺
公开(公告)号：US20070148919A1
公开(公告)日：2007-06-28
申请号：US11313768
申请日：2005-12-22
申请人： Li-Te Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02661
摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.
摘要翻译：一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层，使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理气体包括盐酸盐以第二流量。第一流速基本上低于第二流量。

4. 发明授权

US07175709B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07175709B2
公开(公告)日：2007-02-13
申请号：US10847099
申请日：2004-05-17
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： C30B25/04
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

5. 发明申请

US20070010051A1 Method of forming a MOS device with an additional layer 有权
标题翻译：用附加层形成MOS器件的方法
公开(公告)号：US20070010051A1
公开(公告)日：2007-01-11
申请号：US11174683
申请日：2005-07-05
申请人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
发明人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
IPC分类号： H01L21/8234 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
摘要翻译：提供了一种形成MOS器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。结果，泄漏电流降低。使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

6. 发明申请

US20060151808A1 MOSFET device with localized stressor 审中-公开
公开(公告)号：US20060151808A1
公开(公告)日：2006-07-13
申请号：US11034282
申请日：2005-01-12
申请人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L31/109 , H01L21/8234 , H01L21/477
CPC分类号： H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L29/165 , H01L29/45 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

7. 发明授权

US6041452A Water-saving toilet 失效
标题翻译：节水马桶
公开(公告)号：US6041452A
公开(公告)日：2000-03-28
申请号：US221087
申请日：1998-12-24
申请人： Chien-Liang Hsiao , Pang-Yen Tsai
发明人： Chien-Liang Hsiao , Pang-Yen Tsai
IPC分类号： E03D1/14
CPC分类号： E03D1/145
摘要： A toilet water tank is provided with a water discharging seat which is in turn provided in the top thereof with an upright tube, a high water discharging port and a low water discharging port. The high and the low water discharging ports are movably covered with a cover respectively. The cover is fastened with the upright tube which is provided with a guide wheel member. A flush handle is located outside the toilet water tank such that the flush handle is connected with a control rod extending to the water discharging seat for locating two chains between the two covers and the control rods. The chains are located by the clamps such that the chains can be installed or replaced with ease and speed.
摘要翻译：厕所水箱设有排水座，排水座又在其顶部设置有直立管，高排水口和低排水口。高排水口和低排水口分别用盖子可移动地覆盖。盖子用设有导向轮构件的立管固定。冲水手柄位于马桶水箱外面，使得冲水手柄与延伸到排水座的控制杆连接，用于在两个盖和控制杆之间定位两条链条。链条由夹具定位，使得链条可以方便和快速地安装或更换。

8. 发明授权

US08507951B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US08507951B2
公开(公告)日：2013-08-13
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

9. 发明申请

US20130130184A1 Apparatus and Method for Controlling Wafer Temperature 审中-公开
标题翻译：用于控制晶片温度的装置和方法
公开(公告)号：US20130130184A1
公开(公告)日：2013-05-23
申请号：US13301501
申请日：2011-11-21
申请人： Chang-Shen Lu , Tze-Liang Lee , Yi-Hung Lin , Tai-Chun Huang , Pang-Yen Tsai , Jr-Hung Li
发明人： Chang-Shen Lu , Tze-Liang Lee , Yi-Hung Lin , Tai-Chun Huang , Pang-Yen Tsai , Jr-Hung Li
IPC分类号： F27D21/00
CPC分类号： F27D21/00 , H01L21/67115 , H01L21/67248
摘要： A wafer temperature control apparatus comprises a first temperature sensor and a second temperature sensor. The first temperature sensor is configured to receive a first temperature signal from a center portion of a backside of a susceptor. The second temperature sensor is configured to receive a second temperature signal from an edge portion of the susceptor. A plurality of controllers are configured to adjust each heating source's output based upon the first temperature signal and the second temperature signal.
摘要翻译：晶片温度控制装置包括第一温度传感器和第二温度传感器。第一温度传感器被配置为从基座的背面的中心部分接收第一温度信号。第二温度传感器构造成从基座的边缘部分接收第二温度信号。多个控制器被配置为基于第一温度信号和第二温度信号来调节每个加热源的输出。

10. 发明申请

US20120138897A1 SOURCE/DRAIN STRESSOR HAVING ENHANCED CARRIER MOBILITY AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：具有增强载体移动性的源/排水压力机及其制造方法
公开(公告)号：US20120138897A1
公开(公告)日：2012-06-07
申请号：US12960237
申请日：2010-12-03
申请人： Chin-Hsiang Lin , Jeff J. Xu , Pang-Yen Tsai
发明人： Chin-Hsiang Lin , Jeff J. Xu , Pang-Yen Tsai
IPC分类号： H01L29/165 , H01L21/205
CPC分类号： H01L29/66575 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/7849
摘要： Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.
摘要翻译：公开了可以增强载流子迁移率的各种源极/漏极应力源及其制造方法。示例性源极/漏极应力器包括设置在第二材料的衬底上的第一材料的种子层，第一材料不同于第二材料; 设置在种子层上的松弛外延层; 以及设置在松弛外延层上的外延层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式