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1. 发明授权

US07649233B2 High performance transistor with a highly stressed channel 有权
标题翻译：具有高应力通道的高性能晶体管
公开(公告)号：US07649233B2
公开(公告)日：2010-01-19
申请号：US11950467
申请日：2007-12-05
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

2. 发明授权

US07355235B2 Semiconductor device and method for high-k gate dielectrics 有权
标题翻译：用于高k栅极电介质的半导体器件和方法
公开(公告)号：US07355235B2
公开(公告)日：2008-04-08
申请号：US11020377
申请日：2004-12-22
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L27/108
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L29/1054 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.
摘要翻译：描述了包括高k栅极电介质的半导体器件和工艺。提供衬底，并且在衬底上沉积高k栅介质材料，优选无定形HfSiON。在优选实施例中，高k电介质材料包括氮。在优选实施例中，使用喷射气相沉积（JVD）在高k电介质材料上沉积氮化硅层。当根据优选实施方案沉积JVD氮化物层时，该层具有低密度的电荷陷阱，与氧化物或氧氮化物相比，其维持可比较的载流子迁移率并提供更好的EOT。形成在高k电介质和栅电极之间的第二含氮层用作扩散阻挡层。它还减少了在高k电介质中与氧空位形成有关的问题，从而使费米能级钉扎最小化。

3. 发明申请

US20070187725A1 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US20070187725A1
公开(公告)日：2007-08-16
申请号：US11788229
申请日：2007-04-19
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L29/768 , H01L27/148
CPC分类号： H01L27/10894 , H01L21/28123 , H01L21/28194 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L21/823857 , H01L21/823864 , H01L21/823878 , H01L27/10873 , H01L29/517
摘要： A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extend beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了用于高k栅介质MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅电极和电介质上，在图案化的栅电极和电介质上形成保护侧壁，该侧壁延伸在电介质的底部下方。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

4. 发明授权

US07253481B2 High performance MOS device with graded silicide 有权
标题翻译：具有分级硅化物的高性能MOS器件
公开(公告)号：US07253481B2
公开(公告)日：2007-08-07
申请号：US11181521
申请日：2005-07-14
申请人： Chih-Hao Wang , Ta-Wei Wang , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Ching-Wei Tsai
IPC分类号： H01L29/772
CPC分类号： H01L29/7843 , H01L29/41766 , H01L29/456 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.
摘要翻译：提供了具有较少的电流拥挤效应的半导体器件及其形成方法。半导体器件包括衬底，衬底上的栅极，沿着栅极的边缘并覆盖衬底的一部分的栅极间隔区，衬底中的扩散区域，其中扩散区域包括第一部分和第二部分之间第一部分和栅极间隔物。扩散区域的第一部分具有凹入的顶表面。半导体器件还包括在扩散区上的硅化物层，以及至少在硅化物层上的覆盖层。盖层向半导体器件的沟道区域提供应变。

5. 发明申请

US20060163672A1 High performance CMOS device design 有权
公开(公告)号：US20060163672A1
公开(公告)日：2006-07-27
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

6. 发明授权

US06552921B2 Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory 有权
标题翻译：电路模拟铁电存储器的极化弛豫现象
公开(公告)号：US06552921B2
公开(公告)日：2003-04-22
申请号：US10050075
申请日：2002-01-15
申请人： Ching-Wei Tsai , Shyue-Yi Lee , Ta-Hui Wang
发明人： Ching-Wei Tsai , Shyue-Yi Lee , Ta-Hui Wang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit has a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. A first electrode of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second electrode of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line.
摘要翻译：一种用于模拟铁电存储器的偏振弛豫现象的电路。该电路具有MOS晶体管，铁电电容器，电容器和松弛电压源。 MOS晶体管的栅极耦合到字线，并且MOS晶体管的源极耦合到位线。铁电电容器的第一电极耦合到MOS晶体管的漏极，并且铁电电容器的第二电极耦合到板线。电容器的第一电极耦合到MOS晶体管的漏极。松弛电压源的第一电极耦合到电容器的第二电极，并且弛豫电压源的第二电极耦合到地。上述电容器的电容选择性地远小于位线的电容。

7. 发明授权

US08933196B2 Peptide chromatographic purification assisted by combining of solubility parameter and solution conformation energy calculations 有权
标题翻译：通过结合溶解度参数和溶液构象能量计算来协助肽色谱纯化
公开(公告)号：US08933196B2
公开(公告)日：2015-01-13
申请号：US13472152
申请日：2012-05-15
申请人： Wen-Yih Chen , Li-Chiao Chang , Ruoh-Chyu Ruaan , Ching-Wei Tsai
发明人： Wen-Yih Chen , Li-Chiao Chang , Ruoh-Chyu Ruaan , Ching-Wei Tsai
IPC分类号： C07K1/14 , C07K1/20
CPC分类号： C07K1/20
摘要： A method of purifying a compound from a mixture through a chromatographic column loaded with a column adsorbent. The method comprises: applying the mixture to the chromatographic column; eluting the mixture with an elution solvent composition; and collecting the compound; wherein at least one of the column adsorbent and elution solvent is selected based on one of solubility parameters of the compound, column adsorbent, elution solvent, and conformation energy of the compound.
摘要翻译：从混合物中通过装有柱吸附剂的色谱柱纯化化合物的方法。该方法包括：将混合物施加到色谱柱上; 用洗脱溶剂组合物洗脱混合物; 并收集该化合物; 其中所述柱吸附剂和洗脱溶剂中的至少一种基于所述化合物的溶解度参数，所述化合物的柱吸附剂，洗脱溶剂和构象能之一来选择。

8. 发明授权

US08507951B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US08507951B2
公开(公告)日：2013-08-13
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

9. 发明申请

US20100049070A1 DEVICE OF IMPROVING AUTOMATIC REAL-TIME HEART RATE VARIABILITY ANALYSIS USING ACCELEROMETER 审中-公开
标题翻译：使用加速度计改善自动实时心率变化分析的设备
公开(公告)号：US20100049070A1
公开(公告)日：2010-02-25
申请号：US12543180
申请日：2009-08-18
申请人： TSAIR KAO , CHING-WEI TSAI
发明人： TSAIR KAO , CHING-WEI TSAI
IPC分类号： A61B5/0402
CPC分类号： A61B5/1118 , A61B5/02405 , A61B5/0404 , A61B5/0456 , A61B5/1123 , A61B2562/0219
摘要： The present invention provides a mobile ECG device by using accelerometer to improve real-time automatic analysis of heart rate variability, comprising: a data storage module; a microprocessor (MCU) module in which data are stored and accessed in the data storage module; an analog-to-digital converter module in which the data are transmitted to the microprocessor (MCU) module; an accelerometer peripheral hardware module in which the data are transmitted to the analog-to-digital converter module; and an electrocardiogram peripheral hardware module in which the data are transmitted to the analog-to-digital converter module.
摘要翻译：本发明提供一种通过使用加速度计来改善心率变异性的实时自动分析的移动ECG装置，包括：数据存储模块; 微处理器（MCU）模块，其中在数据存储模块中存储和访问数据; 模数转换器模块，其中数据被传送到微处理器（MCU）模块; 加速度计外围硬件模块，其中数据被传送到模数转换器模块; 以及心电图外围硬件模块，其中数据被发送到模数转换器模块。

10. 发明授权

US07564108B2 Nitrogen treatment to improve high-k gate dielectrics 有权
标题翻译：氮处理改善高k栅极电介质
公开(公告)号：US07564108B2
公开(公告)日：2009-07-21
申请号：US11115932
申请日：2005-04-27
申请人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/76829 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.
摘要翻译：公开了具有氮化栅极电介质的MOSFET及其制造。该方法包括提供衬底并在衬底上沉积非高k电介质材料。非高k电介质包括两层。与衬底相邻的第一层基本上是无氮的，第二层包括约1015个原子/ cm3到约1022个原子/ cm3的氮。 MOSFET还包括在氮化的非高k电介质上的高k电介质材料。高k电介质优选包括HfSiON，ZrSiON或氮化Al 2 O 3。实施例还包括其中核心和外围集成电路区域被分开优化的不对称制造技术。

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