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    • 1. 发明授权
    • High performance transistor with a highly stressed channel
    • 具有高应力通道的高性能晶体管
    • US07649233B2
    • 2010-01-19
    • US11950467
    • 2007-12-05
    • Chih-Hao WangChing-Wei TsaiTa-Wei Wang
    • Chih-Hao WangChing-Wei TsaiTa-Wei Wang
    • H01L27/088
    • H01L29/1054H01L29/665H01L29/6653H01L29/6656H01L29/6659H01L29/66636H01L29/7834H01L29/7843
    • A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
    • 提供具有高应力沟道区的MOS晶体管及其形成方法。 该方法包括在半导体衬底上形成第一半导体板,在第一半导体板上形成第二半导体板,其中第一半导体板具有比第二半导体板大得多的晶格常数,以及在第一半导体板上形成栅叠层 第二半导体板。 第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。 该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层,形成间隔物,LDD区和源极/漏极区,以及形成硅化物区和接触蚀刻 停止层。 在通道区域产生高应力。 由于硅化物区域的增加,电流拥挤效应降低。
    • 2. 发明授权
    • Semiconductor device and method for high-k gate dielectrics
    • 用于高k栅极电介质的半导体器件和方法
    • US07355235B2
    • 2008-04-08
    • US11020377
    • 2004-12-22
    • Chih-Hao WangChing-Wei TsaiShang-Chih Chen
    • Chih-Hao WangChing-Wei TsaiShang-Chih Chen
    • H01L27/108
    • H01L29/517H01L21/28194H01L21/28202H01L29/1054H01L29/513H01L29/518H01L29/78
    • A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.
    • 描述了包括高k栅极电介质的半导体器件和工艺。 提供衬底,并且在衬底上沉积高k栅介质材料,优选无定形HfSiON。 在优选实施例中,高k电介质材料包括氮。 在优选实施例中,使用喷射气相沉积(JVD)在高k电介质材料上沉积氮化硅层。 当根据优选实施方案沉积JVD氮化物层时,该层具有低密度的电荷陷阱,与氧化物或氧氮化物相比,其维持可比较的载流子迁移率并提供更好的EOT。 形成在高k电介质和栅电极之间的第二含氮层用作扩散阻挡层。 它还减少了在高k电介质中与氧空位形成有关的问题,从而使费米能级钉扎最小化。
    • 6. 发明授权
    • Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory
    • 电路模拟铁电存储器的极化弛豫现象
    • US06552921B2
    • 2003-04-22
    • US10050075
    • 2002-01-15
    • Ching-Wei TsaiShyue-Yi LeeTa-Hui Wang
    • Ching-Wei TsaiShyue-Yi LeeTa-Hui Wang
    • G11C1122
    • G11C11/22
    • A circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit has a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. A first electrode of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second electrode of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line.
    • 一种用于模拟铁电存储器的偏振弛豫现象的电路。 该电路具有MOS晶体管,铁电电容器,电容器和松弛电压源。 MOS晶体管的栅极耦合到字线,并且MOS晶体管的源极耦合到位线。 铁电电容器的第一电极耦合到MOS晶体管的漏极,并且铁电电容器的第二电极耦合到板线。 电容器的第一电极耦合到MOS晶体管的漏极。 松弛电压源的第一电极耦合到电容器的第二电极,并且弛豫电压源的第二电极耦合到地。 上述电容器的电容选择性地远小于位线的电容。
    • 8. 发明授权
    • High performance CMOS device design
    • 高性能CMOS器件设计
    • US08507951B2
    • 2013-08-13
    • US12330961
    • 2008-12-09
    • Chih-Hao WangShang-Chih ChenChing-Wei TsaiTa-Wei WangPang-Yen Tsai
    • Chih-Hao WangShang-Chih ChenChing-Wei TsaiTa-Wei WangPang-Yen Tsai
    • H01L29/66
    • H01L21/823807H01L21/823814H01L29/1054H01L29/66553H01L29/66636
    • A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
    • 半导体器件包括栅极,栅极包括位于栅极电极下方的栅极电极和栅极电介质,形成在栅极电极和栅极电介质的侧壁上的间隔物,缓冲层,其具有位于栅极电介质下方的第一部分和间隔物 以及与间隔物相邻的第二部分,其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷,并且基本上与间隔物对准的源极/漏极区域。 缓冲层优选具有比下面的半导体衬底更大的晶格常数。 半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层,其中半导体覆盖层具有比缓冲层更小的晶格常数。