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1. 发明授权

US07148561B2 Ball grid array substrate strip with warpage-preventive linkage structure 有权
标题翻译：具有防翘曲连杆结构的球栅阵列基板条
公开(公告)号：US07148561B2
公开(公告)日：2006-12-12
申请号：US09823176
申请日：2001-03-29
申请人： Chien Ping Huang , Tzong Da Ho , Isaac Yu
发明人： Chien Ping Huang , Tzong Da Ho , Isaac Yu
IPC分类号： H01L23/495 , H01L23/04 , H01L23/48
CPC分类号： H01L23/562 , H01L23/49816 , H01L23/4985 , H01L2924/0002 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
摘要： A substrate strip with warpage-preventive linkage structure is proposed for a BGA (Ball Grid Array) application. The proposed substrate strip is composed of a series of substrates, each being used for the construction of an individual unit of a BGA package, and which is characterized by the provision of a warpage-preventive linkage structure, by which each substrate on the substrate strip is supported by means of no more than two tie bars, i.e., either by a two-point linkage structure or a one-point linkage structure, in contrast to the four-point linkage structure utilized by the prior art. During high-temperature fabrication steps when the substrate is subjected to thermal stresses, the substrate can freely expand toward the corners where no tie bars are provided; and consequently, it can be unwarped by the thermal stresses. This unwarped substrate allows the subsequently implanted ball grid array thereon to have high coplanarity.
摘要翻译：针对BGA（球栅阵列）应用提出了具有防翘曲连杆结构的基板条。所提出的衬底条由一系列衬底组成，每个衬底用于构造BGA封装的单个单元，其特征在于提供防翘曲连接结构，通过该衬底条可将衬底条上的每个衬底与现有技术所使用的四点连杆结构相比，不受两个连杆的支撑，即通过两点连杆结构或一点连杆结构来支撑。在衬底受到热应力的高温制造步骤期间，衬底可以自由地朝向不设置连接条的角部扩展; 因此，它可能被热应力所束缚。这种未经衬底的衬底允许随后在其上注入的球栅阵列具有高共面性。

2. 发明授权

US06359341B1 Ball grid array integrated circuit package structure 失效
标题翻译：球栅阵列集成电路封装结构
公开(公告)号：US06359341B1
公开(公告)日：2002-03-19
申请号：US09489167
申请日：2000-01-21
申请人： Chien Ping Huang , Kevin Chiang , Tzong Da Ho
发明人： Chien Ping Huang , Kevin Chiang , Tzong Da Ho
IPC分类号： H01L2940
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49816 , H01L23/50 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H05K3/341 , H05K3/3436 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A BGA (Ball Grid Array) integrated circuit package is proposed, which is characterized in the use of a ground metallic layer adhered to a substrate. Moreover, the ground metallic layer can provide the semiconductor chip with a heat-dissipation path, allowing heat from the semiconductor chip during operation to be dissipated to the atmosphere via the ground metallic layer, so that the overall heat-dissipation efficiency can be increased. The ground metallic layer is formed with a chip-receiving cavity for accommodating a semiconductor chip mounted on the substrate. As the semiconductor chip is surrounded and in close proximity to the ground metallic layer, it can help reduce undesired simultaneous switching noise, crosstalk, and electromagnetic interference in the integrated circuit package.
摘要翻译：提出了一种BGA（球栅阵列）集成电路封装，其特征在于使用附着在基板上的接地金属层。此外，接地金属层可以为半导体芯片提供散热路径，允许来自半导体芯片的工作中的热量经由接地金属层散发到大气中，从而可以提高总的散热效率。接地金属层形成有用于容纳安装在基板上的半导体芯片的芯片接收腔。当半导体芯片被围绕并且紧邻接地金属层时，它可以帮助减少集成电路封装中的不期望的同时开关噪声，串扰和电磁干扰。

3. 发明授权

US06444498B1 Method of making semiconductor package with heat spreader 有权
标题翻译：用散热器制造半导体封装的方法
公开(公告)号：US06444498B1
公开(公告)日：2002-09-03
申请号：US09990752
申请日：2001-11-15
申请人： Chien Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
发明人： Chien Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
IPC分类号： H01L2144
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L23/4334 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599 , H01L2224/0401
摘要： A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.
摘要翻译：提供了一种制造具有散热器的半导体封装的方法，其中由多个阵列布置的芯片载体组成的芯片载体模块板在每个芯片载体上安装有至少一个芯片。散热器模块板附接到芯片，其中界面层形成在散热器模块板的顶表面上。芯片载体模块板，芯片和散热器模块板被封装。界面层与密封剂之间的粘附力大于界面层与散热器模块板之间的粘合力，界面层与散热器模块板之间的粘合力小于散热器模块板与密封剂之间的粘附力。

4. 发明授权

US06443351B1 Method of achieving solder ball coplanarity on ball grid array integrated circuit package 有权
标题翻译：在球栅阵列集成电路封装上实现焊球共面性的方法
公开(公告)号：US06443351B1
公开(公告)日：2002-09-03
申请号：US09579992
申请日：2000-05-26
申请人： Chien Ping Huang , Tzong Da Ho
发明人： Chien Ping Huang , Tzong Da Ho
IPC分类号： B23K3102
CPC分类号： B23K3/0623 , B23K2101/42 , H01L2224/0401 , H01L2224/0603 , H01L2224/14 , H01L2224/1403 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K2201/09381 , H05K2201/094 , H05K2201/0989 , Y02P70/613
摘要： A BGA (Ball Grid Array) package fabrication method is proposed for the purpose of achieving solder ball coplanarity on a warped BGA package, such as a concavely-warped BGA package or a convexly-warped BGA package. The proposed method is characterized in the provision of a plurality of variably-sized solder-ball pads over the bottom surface of the substrate, each solder-ball pad having a specified size predetermined in accordance with pre-measured package warpage and predetermined relation of solder ball height against pad size. This provision allows the use of a solder mask having fixed-size openings, as contrary to the prior art that uses a solder mask having variably-sized openings, to allow the implanted solder balls to achieve coplanarity and have strengthened shear for robust solder joint.
摘要翻译：提出了一种BGA（球栅阵列）封装制造方法，用于在翘曲的BGA封装上实现焊球共面性，例如凹曲面BGA封装或凸翘曲BGA封装。所提出的方法的特征在于在衬底的底表面上设置多个可变尺寸的焊球焊盘，每个焊球垫具有根据预测的封装翘曲和预定的焊料关系预定的规定尺寸球高度抵抗垫尺寸。这种设置允许使用具有固定尺寸开口的焊接掩模，这与使用具有可变尺寸开口的焊接掩模的现有技术相反，以允许注入的焊球实现共面性并且具有用于坚固的焊接接头的加强的剪切。

5. 发明授权

US06507104B2 Semiconductor package with embedded heat-dissipating device 有权
标题翻译：半导体封装带嵌入式散热装置
公开(公告)号：US06507104B2
公开(公告)日：2003-01-14
申请号：US09905754
申请日：2001-07-14
申请人： Tzong Da Ho , Chien Ping Huang
发明人： Tzong Da Ho , Chien Ping Huang
IPC分类号： H01L2334
CPC分类号： H01L24/73 , H01L23/3107 , H01L23/3128 , H01L23/4334 , H01L23/49503 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73221 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599 , H01L2224/0401
摘要： A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads formed on the heat sink is mounted on a substrate by reflowing the connecting bumps to ball pads of the substrate. The connecting bumps and the ball pads help buffer a clamping force generated during the molding process, so as to prevent a packaged semiconductor chip from being cracked. Moreover, the reflowing process allows the connecting bumps to be self-aligned on the substrate, so as to assure the toning and planarity of the heat sink mounted thereon. Accordingly, during molding, the precisely-positioned beat sink can have its upper side closely abutting an upper mold, allowing a molding resin to be prevented from flashing on the upper side thereof i.e. an exposed side of the heat sink to the atmosphere, so that the heat-dissipating efficiency is increase and the semiconductor package is more cost-effective to fabricate.
摘要翻译：提出了一种具有嵌入式散热装置的半导体封装。包括散热器和附接到形成在散热器上的连接焊盘的多个连接凸块的散热装置通过将连接凸块回流到衬底的球垫而安装在衬底上。连接凸块和球垫有助于缓冲在模制过程中产生的夹紧力，以防止封装的半导体芯片破裂。此外，回流工艺允许连接凸块在基板上自对准，以确保安装在其上的散热器的调色和平面性。因此，在成型期间，精确定位的打纬槽可以使其上侧紧贴在上模上，从而防止模塑树脂在其上侧即散热片暴露的一面到大气中闪烁，使得散热效率提高，制造半导体封装更具成本效益。

6. 发明申请

US20060231944A1 Thermally enhanced semiconductor package and fabrication method thereof 审中-公开
标题翻译：热增强半导体封装及其制造方法
公开(公告)号：US20060231944A1
公开(公告)日：2006-10-19
申请号：US11404674
申请日：2006-04-14
申请人： Chien Ping Huang , Chih Ming Huang
发明人： Chien Ping Huang , Chih Ming Huang
IPC分类号： H01L23/34
CPC分类号： H01L23/3128 , H01L21/4878 , H01L21/6835 , H01L23/367 , H01L23/4334 , H01L24/48 , H01L24/97 , H01L2224/16 , H01L2224/16225 , H01L2224/48227 , H01L2224/4824 , H01L2224/73204 , H01L2224/73253 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/18301 , H01L2224/85 , H01L2224/81 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A thermally enhanced semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a chip carrier. A receiving plate having an opening is provided on the chip carrier and the semiconductor chip is received in the opening. A heat sink formed with an interface layer on a surface thereof is attached via another surface thereof to the semiconductor chip. An encapsulant encapsulating the heat sink, the semiconductor chip and a portion of the receiving plate is formed. A cutting process is performed to cut along edges of the opening of the receiving plate to remove the receiving plate and a portion of the encapsulant formed on the receiving plate. A portion of the encapsulant formed on the interface layer is removed. This allows heat produced by the semiconductor chip to be effectively dissipated by the heat sink.
摘要翻译：提供一种热增强型半导体封装及其制造方法。半导体芯片安装并电连接到芯片载体。具有开口的接收板设置在芯片载体上，并且半导体芯片被接收在开口中。在其表面上形成有界面层的散热器经由其另一表面附接到半导体芯片。形成封装散热器，半导体芯片和接收板的一部分的密封剂。执行切割处理以切割接收板的开口的边缘，以去除接收板和形成在接收板上的一部分密封剂。除去形成在界面层上的一部分密封剂。这使得由半导体芯片产生的热能被散热器有效地消散。

7. 发明授权

US06891273B2 Semiconductor package and fabrication method thereof 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US06891273B2
公开(公告)日：2005-05-10
申请号：US10404173
申请日：2003-04-01
申请人： Han-Ping Pu , Chien Ping Huang
发明人： Han-Ping Pu , Chien Ping Huang
IPC分类号： H01L21/60 , H01L23/31 , H01L23/538 , H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/16 , H01L2224/24011 , H01L2224/24226 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/3025 , H01L2224/82 , H01L2924/00 , H01L2224/05647 , H01L2924/00014 , H01L2224/05655 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171
摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.
摘要翻译：提供了一种半导体封装及其制造方法，其中芯片安装在基板上，并且电介质层被施加在基板和芯片上，具有形成在基板上的结合指状物，并且形成在芯片上的电触点暴露在外部。在电介质层和暴露的结合指状物和电触点之上形成金属层，并且被图案化以形成将芯片的电触头电连接到衬底的结合指的多个导电迹线。导电迹线取代了传统的引线键合技术，从而消除了制造工艺中线扫或短路的发生。因此，可以使用在相邻的电触点之间具有减小的间距的低轮廓芯片，而不限于引线接合技术的可行性。

8. 发明授权

US06743706B2 Integrated circuit package configuration having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body 有权
标题翻译：集成电路封装结构，其具有带法兰部分的封装体和用于模制封装体的封装模具
公开(公告)号：US06743706B2
公开(公告)日：2004-06-01
申请号：US10163060
申请日：2002-06-05
申请人： Chien Ping Huang
发明人： Chien Ping Huang
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L23/3128 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body. This benefit allows the clamping force from the two molds to be reduced to a lower level; and therefore, it would not cause the undesired forming of micro-cracks in the substrate that would otherwise occur in the case of the prior art where a larger clamping force is required to prevent flash. The manufactured integrated circuit package is therefore more assured in quality and reliability. Moreover, the manufacture process can be more simplified to save manufacture cost.
摘要翻译：提出一种集成电路封装，其具有带凸缘部分的封装体和用于模制封装体的封装模具。所提出的包封模具的特征在于，形成在上模具中的封装体腔体还包括在其边缘中的收缩的切口部分。收缩的切口部分可以是均匀的或者形成在多级阶梯式像形状。在模塑过程中，用于形成封装体的树脂将流入该收缩的切口部分; 并且在收缩的切口部分内，树脂将更快地吸收上模的热量，从而增加其粘度并延缓其流动速度。结果，树脂不太可能闪烁到超过封装体的基板的那些表面部分上。这个优点使得来自两个模具的夹紧力可以降低到较低的水平; 因此，在现有技术的情况下，如果需要较大的夹紧力来防止闪光，则不会导致在基板中不期望的形成微裂纹。因此，制造的集成电路封装在质量和可靠性方面更加确保。此外，制造过程可以更加简化以节省制造成本。

9. 发明授权

US06528722B2 Ball grid array semiconductor package with exposed base layer 有权
标题翻译：球栅阵列半导体封装，具有暴露的基极层
公开(公告)号：US06528722B2
公开(公告)日：2003-03-04
申请号：US09235095
申请日：1999-01-21
申请人： Chien Ping Huang , Randy H. Y. Lo
发明人： Chien Ping Huang , Randy H. Y. Lo
IPC分类号： H01L2328
CPC分类号： H05K13/0465 , H01L21/565 , H01L23/3114 , H01L23/4951 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/32014 , H01L2224/32225 , H01L2224/45144 , H01L2224/4824 , H01L2224/48247 , H01L2224/73215 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： A Ball Grid Array (BGA) semiconductor package with exposed base layer includes a base layer having an opening portion in the center thereof and formed with a plurality of holes about the opening portion. A plurality of leads are attached to a second surface of the base layer and each of the leads is connected to a corresponding hole in the base layer. A semiconductor chip is attached and electrically connected to the leads. The semiconductor chip and the leads are covered by an encapsulant formed by an encapsulating compound, leaving a first surface of the base layer exposed. A plurality of solder balls are planted in the holes in the base layer, which are electrically bonded to the leads so as to electrically connect the semiconductor chip to external devices. In this BGA semiconductor package, the leads together with the base layer are used as a substrate for the semiconductor chip to attach thereto. Therefore, there is no need of costly BGA substrate.
摘要翻译：具有暴露基层的球栅阵列（BGA）半导体封装包括在其中心具有开口部分并且围绕开口部分形成有多个孔的基层。多个引线附接到基层的第二表面，并且每个引线连接到基层中的对应的孔。半导体芯片被附接并电连接到引线。半导体芯片和引线被由封装化合物形成的密封剂覆盖，留下基底层的第一表面露出。多个焊球被种植在基底层的孔中，电焊接到引线上，以将半导体芯片电连接到外部装置。在该BGA半导体封装中，将引线与基极层一起用作半导体芯片附着于其上的基板。因此，不需要昂贵的BGA基板。

10. 发明授权

US07342318B2 Semiconductor package free of substrate and fabrication method thereof 有权
标题翻译：不含衬底的半导体封装及其制造方法
公开(公告)号：US07342318B2
公开(公告)日：2008-03-11
申请号：US11112145
申请日：2005-04-21
申请人： Chien Ping Huang , Yu-Po Wang , Chih-Ming Huang
发明人： Chien Ping Huang , Yu-Po Wang , Chih-Ming Huang
IPC分类号： H01L29/40
CPC分类号： H01L21/4857 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L23/3121 , H01L23/58 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68345 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H05K3/007 , H05K3/3457 , H05K3/4682 , H05K2203/0152 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
摘要翻译：提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

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