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1. 发明授权

US07776713B2 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US07776713B2
公开(公告)日：2010-08-17
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/465
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

2. 发明申请

US20080299741A1 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US20080299741A1
公开(公告)日：2008-12-04
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/762 , C09K13/08 , H01L21/31
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

3. 发明授权

US07442620B2 Methods for forming a trench isolation structure with rounded corners in a silicon substrate 有权
标题翻译：在硅衬底中形成具有圆角的沟槽隔离结构的方法
公开(公告)号：US07442620B2
公开(公告)日：2008-10-28
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

4. 发明申请

US20070287260A1 METHODS FOR FORMING AN ISOLATION STRUCTURE IN A SILICON SUBSTRATE 有权
标题翻译：在硅衬底中形成隔离结构的方法
公开(公告)号：US20070287260A1
公开(公告)日：2007-12-13
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

5. 发明授权

US08211806B2 Method of fabricating integrated circuit with small pitch 有权
标题翻译：制造小间距集成电路的方法
公开(公告)号：US08211806B2
公开(公告)日：2012-07-03
申请号：US11846900
申请日：2007-08-29
申请人： Chia-Wei Wu , Ling-Wu Yang
发明人： Chia-Wei Wu , Ling-Wu Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.
摘要翻译：制造具有小间距的集成电路的方法包括提供图案化以形成具有特征之间的开口的至少两个特征的第二材料层。第二材料层形成在第一材料层上并且第一材料层在衬底之上。该方法还包括提供第一氧化物层以形成围绕每个特征的第一侧壁，以及在第一侧壁和第一材料层之上提供第二氧化物层。形成围绕每个特征的第二侧壁。该方法还包括在第二氧化物层上提供导电层，并移除第二侧壁下方的导电层，第二侧壁和第一材料。

6. 发明授权

US07898274B2 Structure of probe 有权
标题翻译：探头结构
公开(公告)号：US07898274B2
公开(公告)日：2011-03-01
申请号：US11745463
申请日：2007-05-08
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R31/20
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test.
摘要翻译：分离式探头用于与待测物体接触以检测其电气特性。本发明提供的探针具有用于与待测物体接触的接触头，以及第一针体和第二针体。第一针体连接到接触头，以将测试信号传送到被测物体进行检测。此外，第二针体还连接到接触头，以通过测试信号传输由被测物体产生的响应信号，以获得被测物体的电特性。

7. 发明授权

US07795088B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US07795088B2
公开(公告)日：2010-09-14
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer. Subsequently, a gate is formed on the substrate and straddles the protection layer, the charge trapping structures and the fin structure. Afterward, source/drain regions are formed in the fin-structure exposed by both sides of the gate.
摘要翻译：提供一种用于制造存储器单元的方法。首先，提供衬底，其中衬底层和材料层已经顺序形成在衬底上。此后，在衬底上形成图案化掩模层。然后，修整图案化的掩模层。随后，通过使用图案化掩模层作为掩模来去除材料层的一部分，衬垫层的一部分和衬底的一部分，以在衬底中限定多个鳍结构。之后，去除图案化的掩模层，并且形成翅片结构中的多个隔离结构。隔离结构的表面比翅片结构的表面低。之后，在基片上形成电荷俘获结构，覆盖翅片结构。成功地，去除一部分电荷捕获结构以暴露材料层。然后，处理过程将材料层转变成保护层。随后，在基板上形成栅极，跨越保护层，电荷捕获结构和鳍结构。之后，源极/漏极区域形成在由栅极两侧暴露的鳍状结构中。

8. 发明授权

US07521321B2 Method of fabricating a non-volatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US07521321B2
公开(公告)日：2009-04-21
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

9. 发明申请

US20080164513A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非挥发性半导体存储器件以及制造非易失性半导体存储器件的方法
公开(公告)号：US20080164513A1
公开(公告)日：2008-07-10
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lal , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lal , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

10. 发明申请

US20060148197A1 Method for forming shallow trench isolation with rounded corners by using a clean process 审中-公开
标题翻译：通过使用清洁工艺形成具有圆角的浅沟槽隔离的方法
公开(公告)号：US20060148197A1
公开(公告)日：2006-07-06
申请号：US11134372
申请日：2005-05-23
申请人： Chia-Wei Wu , Cheng-Shun Chen , Jung-Yu Hsieh , Ling Yang
发明人： Chia-Wei Wu , Cheng-Shun Chen , Jung-Yu Hsieh , Ling Yang
IPC分类号： H01L21/76 , H01L21/302
CPC分类号： H01L21/30608 , H01L21/76232
摘要： In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a trench, a liner oxide is formed over the trench, an STI insulator is formed in the trench, and the hard mask and the pad oxide are removed. Before the formation of the liner oxide, a clean process is performed that comprises applying silicon-consuming solution to round the top corners of the trench.
摘要翻译：在用于在衬底上具有衬垫氧化物的硅衬底中形成STI的方法中，在衬垫氧化物上方形成硬掩模，对硬掩模和衬垫氧化物进行构图以形成开口，通过开口蚀刻硅衬底为了形成沟槽，在沟槽上形成衬垫氧化物，在沟槽中形成STI绝缘体，并且去除硬掩模和衬垫氧化物。在形成衬垫氧化物之前，执行清洁工艺，其包括将消耗硅消耗溶液施加到沟槽的顶角四周。

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