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1. 发明申请

US20050101083A1 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing 审中-公开
公开(公告)号：US20050101083A1
公开(公告)日：2005-05-12
申请号：US10995849
申请日：2004-11-23
申请人： Chew Ang , Eng-Hua Lim , Randall Cha , Jia Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew Ang , Eng-Hua Lim , Randall Cha , Jia Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L21/268 , H01L21/28 , H01L21/8238 , H01L29/49
CPC分类号： H01L29/4933 , H01L21/268 , H01L21/28061 , H01L21/823842
摘要： A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

2. 发明授权

US06828082B2 Method to pattern small features by using a re-flowable hard mask 有权
标题翻译：通过使用可重新流动的硬掩模来绘制小特征的方法
公开(公告)号：US06828082B2
公开(公告)日：2004-12-07
申请号：US10072102
申请日：2002-02-08
申请人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： G03F700
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.
摘要翻译：一种形成小特征的方法，包括以下步骤。提供其上形成有介电层的基板。在电介质层上形成间隔层。间隔层的厚度等于要形成的小特征的厚度。在间隔层上形成图案化的可重新流动的掩模层。掩模层具有宽度“L”的第一开口。图案化的可再流过的掩模层被再流动以形成具有较低宽度“1”的具有再流动的第一开口的图案化的再流过的掩蔽层。再流通的第一开口下部宽度“1”小于预先回流的第一开口宽度“L”。使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“1”的宽度的第二开口。去除图案化的再流过的掩蔽层。然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

3. 发明授权

US06610604B1 Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask 有权
标题翻译：通过使用自对准反向间隔件作为硬掩模形成小晶体管栅极的方法
公开(公告)号：US06610604B1
公开(公告)日：2003-08-26
申请号：US10068053
申请日：2002-02-05
申请人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L21302
CPC分类号： H01L21/28132
摘要： A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
摘要翻译：一种形成窄门的方法，包括以下步骤。提供具有覆盖的Si 3 N 4或SiO 2 / Si 3 N 4堆叠栅极介电层的衬底。栅极材料层形成在栅极介电层上。在栅极材料层上形成硬掩模层。图案化硬掩模层和栅极材料层以形成硬掩模/栅极材料层堆叠。形成围绕硬掩模/栅极材料层叠层的平坦化介电层。图案化的硬掩模层从图案化的栅极材料层上去除以形成具有暴露的电介质层侧壁的空腔。屏蔽间隔物形成在图案化栅极材料层的一部分上的暴露的电介质层侧壁上。使用掩模间隔物作为掩模蚀刻图案化的栅极材料层，以露出栅极电介质层的一部分。去除平坦化的介电层。去除掩模间隔物以形成包括栅极材料的窄门。

4. 发明授权

US06610575B1 Forming dual gate oxide thickness on vertical transistors by ion implantation 有权
标题翻译：通过离子注入在垂直晶体管上形成双栅氧化层厚度
公开(公告)号：US06610575B1
公开(公告)日：2003-08-26
申请号：US10161818
申请日：2002-06-04
申请人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L218234
CPC分类号： H01L21/823857 , H01L21/823885
摘要： A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the non-modified surfaces of the at least one of the non-doped outer or inner side walls.
摘要翻译：一种具有双栅极氧化物厚度的结构的方法，包括以下步骤。提供具有第一和第二柱的衬底。第一和第二支柱各自具有外侧壁和内侧壁。至少一个第一和第二支柱的外侧壁或内侧壁中的至少一个被遮蔽，留下第一和第二柱中的至少一个的至少一个外壁或内侧壁暴露。然后通过暴露的外侧壁或内侧壁中的至少一个植入掺杂剂，改变掺杂的暴露的外壁或内侧壁中的至少一个的表面。第一和第二支柱中的至少一个的被掩蔽的外侧壁或内侧壁中的至少一个被遮蔽。栅极氧化物生长在第一和第二柱的外侧壁和内侧壁上，其中生长在掺杂的外壁或内侧壁中的至少一个的改性表面上的栅极氧化物比生长在栅极氧化物上的栅极氧化物厚所述非掺杂外侧壁或内侧壁中的至少一个的未修饰表面。

5. 发明授权

US06841441B2 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing 有权
标题翻译：用于使用溅射金属沉积，金属离子注入或硅注入的CMOS器件和激光退火的双栅极（一个金属和一个多晶硅或金属硅化物）的制造方法
公开(公告)号：US06841441B2
公开(公告)日：2005-01-11
申请号：US10338156
申请日：2003-01-08
申请人： Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L21/268 , H01L21/28 , H01L21/8238 , H01L29/49
CPC分类号： H01L29/4933 , H01L21/268 , H01L21/28061 , H01L21/823842
摘要： A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
摘要翻译：一种制造第一和第二栅极的方法，包括以下步骤。提供了其上形成有栅介电层的基板。衬底具有第一栅极区域和第二栅极区域。在栅极电介质层上形成薄的第一栅极层。第二栅极区域内的薄的第一栅极层被掩蔽以暴露第一栅极区域内的薄的第一栅极层的一部分。薄的第一栅极层的暴露部分被转换成薄的第三栅极层部分。在薄的第一和第三栅极层部分上形成第二栅极层。第二栅极层和第一和第三栅极层部分被图案化以在第一栅极区域内形成第一栅极，在第二栅极区域内形成第二栅极。

6. 发明申请

US20050089777A1 Method to pattern small features by using a re-flowable hard mask 审中-公开
标题翻译：通过使用可再流动的硬掩模来绘制小特征的方法
公开(公告)号：US20050089777A1
公开(公告)日：2005-04-28
申请号：US10988349
申请日：2004-11-12
申请人： Chew-Hoe Ang , Eng Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： G03C5/00 , G03F7/00 , G03F7/26 , H01L21/033 , H01L21/311 , H01L21/76
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.
摘要翻译：一种形成小特征的方法，包括以下步骤。提供其上形成有介电层的基板。在电介质层上形成间隔层。间隔层的厚度等于要形成的小特征的厚度。在间隔层上形成图案化的可重新流动的掩模层。掩模层具有宽度“L”的第一开口。图案化的可重新流动的掩模层被再流动以形成具有较低宽度“l”的具有再流动的第一开口的图案化的再流过的掩蔽层。再流出的第一开口下部宽度“l”小于预先流动的第一开口宽度“L”。使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层上，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“l”的宽度的第二开口。去除图案化的再流过的掩蔽层。然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

7. 发明授权

US06605501B1 Method of fabricating CMOS device with dual gate electrode 失效
标题翻译：制造具有双栅电极的CMOS器件的方法
公开(公告)号：US06605501B1
公开(公告)日：2003-08-12
申请号：US10163667
申请日：2002-06-06
申请人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou
发明人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L21/823842 , H01L21/823864 , Y10S438/981
摘要： A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar. The thinner first preliminary gate oxide is removed from over the first pillar and the thicker second preliminary gate oxide is thinned from over the second pillar. First final gate oxide is formed over the first pillar and second final gate oxide is formed on the second pillar. The second final gate oxide including the thinned second preliminary gate oxide. The second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.
摘要翻译：一种制造双栅极氧化物厚度的方法，包括以下步骤。提供具有第一支柱和第二支柱的基板。栅极电介质层形成在衬底和第一和第二柱上。第一和第二薄间隔物分别形成在第一和第二柱的覆盖侧壁的栅介质层上。第二支柱被掩盖，留下第一支柱。第一个薄的间隔件从未掩模的第一支柱上移除。从掩蔽的第二支柱上取下掩模。该结构被氧化以将第二薄间隔物转移到先前掩蔽的第二柱上的第二初步栅极氧化物上，并在未掩模的第一柱上形成第一初步栅极氧化物。第二柱上的第二栅极氧化物比第一柱上的第一栅极氧化物厚。较薄的第一预栅极氧化物从第一柱上方移除，并且较厚的第二预选栅极氧化物从第二柱上方变薄。第一末端栅极氧化物形成在第一柱上，第二最终栅极氧化物形成在第二柱上。第二最终栅极氧化物包括稀化的第二预栅极氧化物。第二柱上的第二最终栅极氧化物比第一柱上的第一最终栅极氧化物厚。

8. 发明授权

US06468851B1 Method of fabricating CMOS device with dual gate electrode 失效
标题翻译：制造具有双栅电极的CMOS器件的方法
公开(公告)号：US06468851B1
公开(公告)日：2002-10-22
申请号：US10038886
申请日：2002-01-02
申请人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia-Zhen Zheng , Elgin Kiok Boone Quek , Mei-Sheng Zhou , Daniel Lee-Wei Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia-Zhen Zheng , Elgin Kiok Boone Quek , Mei-Sheng Zhou , Daniel Lee-Wei Yen
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N+ poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N+ nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N+ poly gate to eliminate a mask level for the dual gate electrodes.
摘要翻译：一种制造具有双栅电极的双栅极CMOS器件的方法。 nOS多晶硅栅极用于nMOSFET，金属栅极用于pMOSFET。可以用高导电金属封装N + nMOSFET多晶硅栅极以降低其栅极电阻。牺牲帽用于N +多晶硅栅极以消除双栅电极的掩模电平。

9. 发明申请

US20050106895A1 Supercritical water application for oxide formation 审中-公开
标题翻译：氧化物形成的超临界水应用
公开(公告)号：US20050106895A1
公开(公告)日：2005-05-19
申请号：US10715326
申请日：2003-11-17
申请人： Yu-Liang Lin , Ping Chuang , Mei-Sheng Zhou
发明人： Yu-Liang Lin , Ping Chuang , Mei-Sheng Zhou
IPC分类号： G06F17/00 , H01L21/31 , H01L21/316 , H01L21/469 , H01L21/76 , H01L21/768
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31675 , H01L21/76801
摘要： The present disclosure provides for a method and system for fabricating an insulating layer on a substrate. The method and system provide a fluid to a substrate, wherein the fluid is provided in an aerosol form. The method and system also provides for generating a supercritical process environment proximate to the substrate. The method and system further provides a proximate supercritical process environment having a supercritical process temperature and a supercritical process pressure for altering the fluid, and placing the substrate in contact with the altered fluid, wherein the insulating layer is formed on the substrate by a reaction between the substrate and the fluid.
摘要翻译：本公开提供了用于在基板上制造绝缘层的方法和系统。该方法和系统向基材提供流体，其中流体以气溶胶形式提供。该方法和系统还提供用于生成靠近基底的超临界过程环境。该方法和系统还提供了一种具有超临界过程温度和超临界过程压力的邻近超临界过程环境，用于改变流体，并使衬底与改变的流体接触，其中绝缘层通过基材和流体。

10. 发明授权

US06358842B1 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics 有权
标题翻译：形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法
公开(公告)号：US06358842B1
公开(公告)日：2002-03-19
申请号：US09633770
申请日：2000-08-07
申请人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
发明人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
IPC分类号： H01L213205
CPC分类号： H01L21/76831 , H01L21/31138 , H01L21/76808
摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
摘要翻译：已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。镶嵌互连可以是单镶嵌或双镶嵌。提供铜导体覆盖在半导体衬底上。第一钝化层被提供在铜导体上。沉积在第一钝化层上的低介电常数层。沉积覆盖在低介电常数层上的可选的覆盖层。沉积在覆盖层上的光致抗蚀剂层。覆盖层和低介电常数层被蚀刻通过以形成通孔。同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。从而防止侧壁弯曲和通过中毒。蚀刻第一钝化层以暴露下面的铜导体。沉积覆盖覆盖层并填充通孔的铜层。铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

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