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1. 发明授权

US06610604B1 Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask 有权
标题翻译：通过使用自对准反向间隔件作为硬掩模形成小晶体管栅极的方法
公开(公告)号：US06610604B1
公开(公告)日：2003-08-26
申请号：US10068053
申请日：2002-02-05
申请人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L21302
CPC分类号： H01L21/28132
摘要： A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
摘要翻译：一种形成窄门的方法，包括以下步骤。提供具有覆盖的Si 3 N 4或SiO 2 / Si 3 N 4堆叠栅极介电层的衬底。栅极材料层形成在栅极介电层上。在栅极材料层上形成硬掩模层。图案化硬掩模层和栅极材料层以形成硬掩模/栅极材料层堆叠。形成围绕硬掩模/栅极材料层叠层的平坦化介电层。图案化的硬掩模层从图案化的栅极材料层上去除以形成具有暴露的电介质层侧壁的空腔。屏蔽间隔物形成在图案化栅极材料层的一部分上的暴露的电介质层侧壁上。使用掩模间隔物作为掩模蚀刻图案化的栅极材料层，以露出栅极电介质层的一部分。去除平坦化的介电层。去除掩模间隔物以形成包括栅极材料的窄门。

2. 发明授权

US06632712B1 Method of fabricating variable length vertical transistors 失效
标题翻译：制造可变长度垂直晶体管的方法
公开(公告)号：US06632712B1
公开(公告)日：2003-10-14
申请号：US10263895
申请日：2002-10-03
申请人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L218238
CPC分类号： H01L29/66666 , H01L21/823885 , H01L29/7827
摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.
摘要翻译：已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

3. 发明授权

US06828082B2 Method to pattern small features by using a re-flowable hard mask 有权
标题翻译：通过使用可重新流动的硬掩模来绘制小特征的方法
公开(公告)号：US06828082B2
公开(公告)日：2004-12-07
申请号：US10072102
申请日：2002-02-08
申请人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： G03F700
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.
摘要翻译：一种形成小特征的方法，包括以下步骤。提供其上形成有介电层的基板。在电介质层上形成间隔层。间隔层的厚度等于要形成的小特征的厚度。在间隔层上形成图案化的可重新流动的掩模层。掩模层具有宽度“L”的第一开口。图案化的可再流过的掩模层被再流动以形成具有较低宽度“1”的具有再流动的第一开口的图案化的再流过的掩蔽层。再流通的第一开口下部宽度“1”小于预先回流的第一开口宽度“L”。使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“1”的宽度的第二开口。去除图案化的再流过的掩蔽层。然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

4. 发明授权

US06610575B1 Forming dual gate oxide thickness on vertical transistors by ion implantation 有权
标题翻译：通过离子注入在垂直晶体管上形成双栅氧化层厚度
公开(公告)号：US06610575B1
公开(公告)日：2003-08-26
申请号：US10161818
申请日：2002-06-04
申请人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L218234
CPC分类号： H01L21/823857 , H01L21/823885
摘要： A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the non-modified surfaces of the at least one of the non-doped outer or inner side walls.
摘要翻译：一种具有双栅极氧化物厚度的结构的方法，包括以下步骤。提供具有第一和第二柱的衬底。第一和第二支柱各自具有外侧壁和内侧壁。至少一个第一和第二支柱的外侧壁或内侧壁中的至少一个被遮蔽，留下第一和第二柱中的至少一个的至少一个外壁或内侧壁暴露。然后通过暴露的外侧壁或内侧壁中的至少一个植入掺杂剂，改变掺杂的暴露的外壁或内侧壁中的至少一个的表面。第一和第二支柱中的至少一个的被掩蔽的外侧壁或内侧壁中的至少一个被遮蔽。栅极氧化物生长在第一和第二柱的外侧壁和内侧壁上，其中生长在掺杂的外壁或内侧壁中的至少一个的改性表面上的栅极氧化物比生长在栅极氧化物上的栅极氧化物厚所述非掺杂外侧壁或内侧壁中的至少一个的未修饰表面。

5. 发明申请

US20050089777A1 Method to pattern small features by using a re-flowable hard mask 审中-公开
标题翻译：通过使用可再流动的硬掩模来绘制小特征的方法
公开(公告)号：US20050089777A1
公开(公告)日：2005-04-28
申请号：US10988349
申请日：2004-11-12
申请人： Chew-Hoe Ang , Eng Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： G03C5/00 , G03F7/00 , G03F7/26 , H01L21/033 , H01L21/311 , H01L21/76
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.
摘要翻译：一种形成小特征的方法，包括以下步骤。提供其上形成有介电层的基板。在电介质层上形成间隔层。间隔层的厚度等于要形成的小特征的厚度。在间隔层上形成图案化的可重新流动的掩模层。掩模层具有宽度“L”的第一开口。图案化的可重新流动的掩模层被再流动以形成具有较低宽度“l”的具有再流动的第一开口的图案化的再流过的掩蔽层。再流出的第一开口下部宽度“l”小于预先流动的第一开口宽度“L”。使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层上，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“l”的宽度的第二开口。去除图案化的再流过的掩蔽层。然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

6. 发明授权

US06605501B1 Method of fabricating CMOS device with dual gate electrode 失效
标题翻译：制造具有双栅电极的CMOS器件的方法
公开(公告)号：US06605501B1
公开(公告)日：2003-08-12
申请号：US10163667
申请日：2002-06-06
申请人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou
发明人： Chew-Hoe Ang , Eng-Hua Lim , Cher-Liang Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L21/823842 , H01L21/823864 , Y10S438/981
摘要： A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar. The thinner first preliminary gate oxide is removed from over the first pillar and the thicker second preliminary gate oxide is thinned from over the second pillar. First final gate oxide is formed over the first pillar and second final gate oxide is formed on the second pillar. The second final gate oxide including the thinned second preliminary gate oxide. The second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.
摘要翻译：一种制造双栅极氧化物厚度的方法，包括以下步骤。提供具有第一支柱和第二支柱的基板。栅极电介质层形成在衬底和第一和第二柱上。第一和第二薄间隔物分别形成在第一和第二柱的覆盖侧壁的栅介质层上。第二支柱被掩盖，留下第一支柱。第一个薄的间隔件从未掩模的第一支柱上移除。从掩蔽的第二支柱上取下掩模。该结构被氧化以将第二薄间隔物转移到先前掩蔽的第二柱上的第二初步栅极氧化物上，并在未掩模的第一柱上形成第一初步栅极氧化物。第二柱上的第二栅极氧化物比第一柱上的第一栅极氧化物厚。较薄的第一预栅极氧化物从第一柱上方移除，并且较厚的第二预选栅极氧化物从第二柱上方变薄。第一末端栅极氧化物形成在第一柱上，第二最终栅极氧化物形成在第二柱上。第二最终栅极氧化物包括稀化的第二预栅极氧化物。第二柱上的第二最终栅极氧化物比第一柱上的第一最终栅极氧化物厚。

7. 发明授权

US06468851B1 Method of fabricating CMOS device with dual gate electrode 失效
标题翻译：制造具有双栅电极的CMOS器件的方法
公开(公告)号：US06468851B1
公开(公告)日：2002-10-22
申请号：US10038886
申请日：2002-01-02
申请人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia-Zhen Zheng , Elgin Kiok Boone Quek , Mei-Sheng Zhou , Daniel Lee-Wei Yen
发明人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia-Zhen Zheng , Elgin Kiok Boone Quek , Mei-Sheng Zhou , Daniel Lee-Wei Yen
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N+ poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N+ nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N+ poly gate to eliminate a mask level for the dual gate electrodes.
摘要翻译：一种制造具有双栅电极的双栅极CMOS器件的方法。 nOS多晶硅栅极用于nMOSFET，金属栅极用于pMOSFET。可以用高导电金属封装N + nMOSFET多晶硅栅极以降低其栅极电阻。牺牲帽用于N +多晶硅栅极以消除双栅电极的掩模电平。

8. 发明授权

US06709912B1 Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization 失效
标题翻译：具有不同Ge浓度的双Si-Ge多晶硅栅极用于CMOS器件优化
公开(公告)号：US06709912B1
公开(公告)日：2004-03-23
申请号：US10266425
申请日：2002-10-08
申请人： Chew-Hoe Ang , Jeffrey Chee Wei-Lun , Wenhe Lin , Jia Zhen Zheng
发明人： Chew-Hoe Ang , Jeffrey Chee Wei-Lun , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , Y10S438/933
摘要： A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si—Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si—Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration. The polycrystalline Si—Ge layer is patterned to form a gate in each of the active areas wherein the gate in the PMOS active area has a higher Ge concentration than the gate in the NMOS active area to complete formation of dual Si—Ge polysilicon gates with different Ge concentrations in the fabrication of an integrated circuit device.
摘要翻译：描述了形成具有不同Ge浓度的双Si-Ge多栅极的方法。在由隔离区隔开的半导体衬底上提供NMOS有源区和PMOS有源区。生长在每个有源区域中的半导体衬底上的栅氧化层。沉积在多晶Si-Ge层具有第一Ge浓度的栅极氧化物层上的多晶硅 - 锗（Si-Ge）层。当PMOS有源区域暴露时，NMOS有源区域被阻塞。进行Ge等离子体掺杂和激光退火到PMOS有源区的连续循环以实现高于第一Ge浓度的第二Ge浓度。多晶Si-Ge层被图案化以在每个有源区域中形成栅极，其中PMOS有源区中的栅极具有比NMOS有源区域中的栅极更高的Ge浓度，以完成双Si-Ge多晶硅栅极的形成，在集成电路器件的制造中不同的Ge浓度。

9. 发明授权

US06403425B1 Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide 有权
标题翻译：双栅极氧化物工艺，由于厚栅氧化物而导致薄栅沟道注入分布的热分布降低
公开(公告)号：US06403425B1
公开(公告)日：2002-06-11
申请号：US09995191
申请日：2001-11-27
申请人： Chew-Hoe Ang , Wenhe Lin , Jia Zhen Zheng
发明人： Chew-Hoe Ang , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L218234
CPC分类号： H01L21/823857
摘要： A new method is provided for the creation of layers of gate oxide of different thicknesses. A substrate is provided, the surface of the substrate is divided into a first surface region over which a thick layer of gate oxide has to be created and a second surface region over which a thin layer of gate oxide is to be created. Thick gate-oxide implants are performed into the surface of the substrate. A thick layer of gate oxide is created over the surface of the substrate, the thick layer of gate oxide is successively patterned for thin gate-oxide implants, comprising thin gate-oxide n-well/p-well, threshold, punchthrough implants, into the second surface region of the substrate. The thick layer of gate oxide is removed from the second surface region of the substrate. The (now contaminated) top layer of the thick layer of gate oxide is removed, a thin layer of gate oxide is grown over the second surface region of the substrate.
摘要翻译：提供了一种新的形成不同厚度栅极氧化层的方法。提供了一种衬底，衬底的表面被分成第一表面区域，在该第一表面区域上必须产生一个厚的栅极氧化层，另一个表面区域将形成一薄层的栅极氧化物。将厚栅氧化物植入物进行到衬底的表面。在衬底的表面上形成厚层栅极氧化物，栅极氧化物的厚层依次构图用于薄栅极氧化物植入物，其包括薄的栅极氧化物n阱/ p阱，阈值穿透植入物衬底的第二表面区域。栅极氧化物的厚层从衬底的第二表面区域去除。去除栅极氧化物的厚层的（现在被污染的）顶层，在衬底的第二表面区域上生长薄层的栅极氧化物。

10. 发明申请

US20060103450A1 Charge pump current source 有权
标题翻译：电荷泵电流源
公开(公告)号：US20060103450A1
公开(公告)日：2006-05-18
申请号：US10991591
申请日：2004-11-18
申请人： Tupei Chen , Chew-Hoe Ang , Shyue-Seng Tan , Jia-Zhen Zheng
发明人： Tupei Chen , Chew-Hoe Ang , Shyue-Seng Tan , Jia-Zhen Zheng
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： This invention provides a circuit and a method for generating a low-level current using semiconductor charge pumping. The invention provides a means of generating a range of current sources by varying the frequency of a repetitive voltage pulse input signal. Also, this invention utilizes one or many MOSFET devices in order to produce higher levels of current. The current source embodiments of this invention generate very stable current sources with high input impedances.
摘要翻译：本发明提供了使用半导体电荷泵浦来产生低电平电流的电路和方法。本发明提供了一种通过改变重复电压脉冲输入信号的频率来产生电流源范围的装置。此外，本发明利用一个或多个MOSFET器件来产生更高的电流。本发明的电流源实施例产生具有高输入阻抗的非常稳定的电流源。

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