专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050064629A1 Tungsten-copper interconnect and method for fabricating the same 审中-公开
标题翻译：钨铜互连及其制造方法
公开(公告)号：US20050064629A1
公开(公告)日：2005-03-24
申请号：US10665309
申请日：2003-09-22
申请人： Chen-Hua Yu , Tsu Shih , Chung-Shi Liu , Shwang-Min Jeng , Horng-Huei Tseng
发明人： Chen-Hua Yu , Tsu Shih , Chung-Shi Liu , Shwang-Min Jeng , Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76829 , H01L21/76834
摘要： An interconnect structure utilizing a silicon carbon-containing film as an interlayer between dielectrics. A semiconductor substrate having a conductor thereon is provided, and an insulating layer overlies the semiconductor substrate. The insulating layer has a via hole therein to expose the conductor. A conductive plug, e.g. a tungsten plug, substantially fills the via hole and electrically connects the underlying conductor. A silicon carbon-containing film and a low k dielectric layer overlie the insulating layer and the conductive plug, and have a trench therein exposing the conductive plug. A copper or copper alloy conductor substantially fills the trench.
摘要翻译：利用含硅碳膜作为电介质之间的中间层的互连结构。设置有其上具有导体的半导体衬底，并且绝缘层覆盖在半导体衬底上。绝缘层在其中具有通孔以露出导体。导电塞，例如。钨插头基本上填充通孔并电连接下面的导体。含硅碳膜和低k电介质层覆盖在绝缘层和导电插塞上，并且在其中具有暴露导电插塞的沟槽。铜或铜合金导体基本上填充沟槽。

2. 发明授权

US06372632B1 Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer 有权
标题翻译：通过使用牺牲氧化物层来消除铜互连的凹陷的方法
公开(公告)号：US06372632B1
公开(公告)日：2002-04-16
申请号：US09490138
申请日：2000-01-24
申请人： Chen-Hua Yu , Weng Chang , Jih-Chung Twu , Tsu Shih
发明人： Chen-Hua Yu , Weng Chang , Jih-Chung Twu , Tsu Shih
IPC分类号： H01L214763
CPC分类号： H01L21/7688 , H01L21/31053 , H01L21/3212 , H01L21/7684
摘要： A method of forming a planarized metal interconnect comprising the following steps. A semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial layer over is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are patterned to form a trench within the sacrificial layer and low K dielectric layer. A barrier layer is formed over the sacrificial layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial layer covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is removed to form a planarized metal interconnect.
摘要翻译：一种形成平面化金属互连的方法，包括以下步骤。提供半导体结构。在半导体结构上形成低K电介质层。在低K电介质层上形成牺牲层。将牺牲层和低K电介质层图案化以在牺牲层和低K电介质层内形成沟槽。在牺牲层上形成阻挡层，衬在沟槽侧壁和底部。金属沉积在阻挡层上以形成填充衬里沟槽的金属层，并覆盖填充覆盖低K电介质层的牺牲层。金属层和阻挡层被平坦化，暴露牺牲层的上表面。去除牺牲层以形成平坦化的金属互连。

3. 发明授权

US06682396B1 Apparatus and method for linear polishing 有权
标题翻译：用于线性抛光的装置和方法
公开(公告)号：US06682396B1
公开(公告)日：2004-01-27
申请号：US09546583
申请日：2000-04-11
申请人： Tsu Shih , Chen-Hua Yu
发明人： Tsu Shih , Chen-Hua Yu
IPC分类号： B24B4900
CPC分类号： B24B37/24 , B24B21/004 , B24B37/26
摘要： A linear polisher for polishing a substrate that always provides a fresh abrasive surface for polishing and a method for linear polishing a substrate are described. In the linear polisher, a length of a polishing pad is supported on a pair of rollers which are driven by a motor means for either intermittently or continuously advancing the pad during a polishing process. A vibration generator which is connected to the polishing pad through an adaptor provides lateral, or vibration in a transverse direction of the pad throughout the polishing process. The present invention novel linear polisher enables substantially constant removal rate to be achieved throughout the pad life of a polishing pad without deterioration such as that normally seen in a conventional rotary or linear CMP apparatus. Optionally, a rotatable substrate holder is utilized to further improve the polishing uniformity of the linear polishing apparatus.
摘要翻译：描述了用于抛光总是提供用于抛光的新鲜研磨表面的基板的线性抛光机和用于线性抛光基板的方法。在线性抛光机中，抛光垫的长度被支撑在一对辊上，该辊由用于在抛光过程中间歇地或连续地推进垫的马达装置驱动。通过适配器连接到抛光垫的振动发生器在整个抛光过程中提供横向或在横向的振动。本发明的新型线性抛光机能够在抛光垫的整个焊盘使用寿命期间实现基本上恒定的去除速率，而不会在常规的旋转或线性CMP设备中通常看到这样的劣化。可选地，可旋转的基板保持器用于进一步改善线性抛光装置的抛光均匀性。

4. 发明授权

US06501186B1 Bond pad having variable density via support and method for fabrication 有权
标题翻译：通过支架具有可变密度的焊盘和用于制造的方法
公开(公告)号：US06501186B1
公开(公告)日：2002-12-31
申请号：US09915035
申请日：2001-07-25
申请人： Chen-Hua Yu , Tsu Shih
发明人： Chen-Hua Yu , Tsu Shih
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/859 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/00
摘要： A bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a different via density than the other and a method for forming the structure are described. The structure includes a layer of an insulating material such as a low-k dielectric, a first multiplicity of vias formed in a center region of the low-k dielectric material that has a first density, a second multiplicity of vias formed in a peripheral region of the low-k dielectric material surrounding the center region that has a second density, wherein the second density is higher than the first density. A conductive metal pad of generally rectangular shape is then formed on top of and electrically connected to the first and second multiplicity of vias.
摘要翻译：描述了由布置在至少两个具有不同的通孔密度的区域中的多个通孔支撑的接合焊盘结构以及用于形成该结构的方法。该结构包括绝缘材料层，例如低k电介质，形成在具有第一密度的低k电介质材料的中心区域中的第一多个通孔，在周边区域中形成的第二多个通孔围绕具有第二密度的中心区域的低k电介质材料，其中第二密度高于第一密度。然后形成大致矩形形状的导电金属焊盘，并且与第一和第二多个通孔电连接。

5. 发明授权

US06458689B2 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE氧化物进行接触或通过照相和氧化物和化学机械抛光剂进行缺陷还原
公开(公告)号：US06458689B2
公开(公告)日：2002-10-01
申请号：US09818714
申请日：2001-03-28
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介质层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在电介质层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

6. 发明授权

US06383935B1 Method of reducing dishing and erosion using a sacrificial layer 有权
标题翻译：使用牺牲层减少凹陷和侵蚀的方法
公开(公告)号：US06383935B1
公开(公告)日：2002-05-07
申请号：US09687162
申请日：2000-10-16
申请人： Cheng Chung Lin , Chen Hua Yu , Tsu Shih , Weng Chang
发明人： Cheng Chung Lin , Chen Hua Yu , Tsu Shih , Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.
摘要翻译：已知化学机械抛光（CMP）在平坦化表面包括部分填充有金属的宽沟槽时引起凹陷。首先用在CMP下的抛光速率与沟槽中的金属相似的材料填充沟槽已经克服了这个问题。旋转涂层用于此，使得只有沟槽被填充。在CMP之后，除去该材料的任何残余物，留下已经被平坦化到预期程度的表面，而不引入显着的凹陷并且金属的最小侵蚀。

7. 发明授权

US6020263A Method of recovering alignment marks after chemical mechanical polishing of tungsten 失效
标题翻译：钨化学机械抛光后恢复对准标记的方法
公开(公告)号：US6020263A
公开(公告)日：2000-02-01
申请号：US742229
申请日：1996-10-31
申请人： Tsu Shih , Chen-Hua Yu
发明人： Tsu Shih , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/64
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002
摘要： This invention describes a method of forming alignment marks which will be preserved after contact holes in a dielectric have been filled with barrier metal and contact metal and the wafer has been planarized. The alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal. The alignment lines and contact holes are filled with metal at the same time. After the wafer has been planarized, using a method such as chemical mechanical polishing, a small thickness of the dielectric is etched back using vertical dry anisotropic etching which will not remove either the contact metal or barrier metal. This leaves barrier metal and contact metal extending above the plane of the dielectric forming alignment marks. These alignment marks are preserved after subsequent processing steps, such as deposition of a layer of electrode metal.
摘要翻译：本发明描述了一种形成对准标记的方法，其将在电介质中的接触孔填充有阻挡金属和接触金属并且晶片已被平坦化之后被保留。通过在形成接触孔时在电介质中形成的对准线填充有阻挡金属和接触金属，形成对准标记。对准线和接触孔同时被金属填充。在晶片平坦化之后，使用诸如化学机械抛光的方法，使用不会去除接触金属或阻挡金属的垂直干燥各向异性蚀刻来回蚀电介质的小厚度。这使得阻挡金属和接触金属在电介质成形对准标记的平面之上延伸。这些对准标记在后续处理步骤之后被保留，例如沉积一层电极金属。

8. 发明授权

US5972798A Prevention of die loss to chemical mechanical polishing 失效
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US5972798A
公开(公告)日：1999-10-26
申请号：US86775
申请日：1998-05-29
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

9. 发明授权

US06444371B1 Prevention of die loss to chemical mechanical polishing 有权
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US06444371B1
公开(公告)日：2002-09-03
申请号：US09377541
申请日：1999-08-19
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

10. 发明授权

US6020249A Method for photo alignment after CMP planarization 失效
公开(公告)号：US6020249A
公开(公告)日：2000-02-01
申请号：US891088
申请日：1997-07-10
申请人： Tsu Shih , Jui-Yu Chang , Syun-Ming Jang , Chen-Hua Yu
发明人： Tsu Shih , Jui-Yu Chang , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： G03F9/00 , H01L23/544 , H01L23/48
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002
摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式