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1. 发明授权

US06624499B2 System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient 有权
标题翻译：通过产生温度梯度增强硅化物电迁移来编程熔丝结构的系统
公开(公告)号：US06624499B2
公开(公告)日：2003-09-23
申请号：US10247415
申请日：2002-09-19
申请人： Chandrasekharan Kothandaraman , S. Sundar Kumar Iyer , Subramanian Iyer , Chandrasekhar Narayan
发明人： Chandrasekharan Kothandaraman , S. Sundar Kumar Iyer , Subramanian Iyer , Chandrasekhar Narayan
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.
摘要翻译：本发明提供一种通过电迁移编程的系统，装置和方法。包括阴极和由具有诸如硅化物之类的导电部件的熔丝连接的阳极的半导体熔丝被耦合到电源。电势通过阴极和阳极施加在导电熔丝连接上，其中电位为大小以引发硅化物从半导体熔丝的区域的电迁移，从而降低熔丝链的导电性。响应于所施加的电位，通过实现熔丝链和阴极和阳极中的一个之间的温度梯度来增强电迁移。半导体保险丝的一部分以热传递关系被选择性地冷却以增加温度梯度。在一个实施例中，将散热器施加到阴极。散热器可以是在与熔丝连接绝缘的情况下紧邻阴极耦合的金属层。在另一个实施方案中，通过选择性地改变下面的氧化物层的厚度使得阴极设置在比熔丝链更薄的氧化物层上来增加温度梯度。

2. 发明授权

US06323535B1 Electrical fuses employing reverse biasing to enhance programming 失效
标题翻译：采用反向偏置的电气保险丝来加强编程
公开(公告)号：US06323535B1
公开(公告)日：2001-11-27
申请号：US09595764
申请日：2000-06-16
申请人： Sundar K. Iyer , Peter Smeys , Chandrasekhar Narayan , Subramanian Iyer , Axel Brintzinger
发明人： Sundar K. Iyer , Peter Smeys , Chandrasekhar Narayan , Subramanian Iyer , Axel Brintzinger
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.
摘要翻译：根据本发明的用于半导体器件的熔丝包括第一掺杂剂类型的第一掺杂剂类型的阴极和包括第二掺杂剂类型的第二掺杂剂类型的阳极。熔丝连接器连接阴极和阳极并且包括第二掺杂剂类型。熔丝链和阴极在它们之间形成一个结，并且该结被配置为相对于阴极电位和阳极电位被反向偏置。导电层跨越结形成，使得在结处流动的电流被转移到导电层中以增强材料迁移以对熔丝进行编程。

3. 发明申请

US20110109998A1 RECORDING HEAD WITH TILTED ORIENTATION 有权
标题翻译：记录头与倾斜方向
公开(公告)号：US20110109998A1
公开(公告)日：2011-05-12
申请号：US12614275
申请日：2009-11-06
申请人： David Berman , Robert G. Biskeborn , Michel Despont , Philipp Herget , Wayne Isami Imaino , Pierre-Olivier Jubert , Peter V. Koeppe , Chandrasekhar Narayan
发明人： David Berman , Robert G. Biskeborn , Michel Despont , Philipp Herget , Wayne Isami Imaino , Pierre-Olivier Jubert , Peter V. Koeppe , Chandrasekhar Narayan
IPC分类号： G11B5/33 , B05D5/12
CPC分类号： G11B5/3163 , G11B5/00826 , G11B5/398
摘要： In one embodiment, a read sensor for a recording head for a magnetic media storage system, has first and second shields, and a magneto-resistive sensor disposed between and shielded by the first and second shields in which the sensing axis of the sensor is tilted with respect to the recording surface of the head. In one embodiment, the sensing axis is oriented at an angle between 10 and 60 degrees with respect to the normal of the recording surface. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，用于磁性介质存储系统的记录头的读取传感器具有第一和第二屏蔽以及设置在第一和第二屏蔽之间并被传感器的感测轴倾斜的屏蔽的磁阻传感器相对于头部的记录表面。在一个实施例中，感测轴相对于记录表面的法线定向成10度至60度的角度。描述和要求保护其他实施例。

4. 发明授权

US07486845B2 Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter 有权
标题翻译：波导偏振分束器及制造波导线栅偏振光束分离器的方法
公开(公告)号：US07486845B2
公开(公告)日：2009-02-03
申请号：US11870463
申请日：2007-10-11
申请人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstorm
发明人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstorm
IPC分类号： G02B6/00 , G02B6/10
CPC分类号： G02B6/126 , B29D11/00759 , G02B6/136 , G02B2006/1215
摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.
摘要翻译：实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点，这将导致轻微的过度损失。在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

5. 发明申请

US20050121711A1 Chip and wafer integration process using vertical connections 有权
公开(公告)号：US20050121711A1
公开(公告)日：2005-06-09
申请号：US11033926
申请日：2005-01-12
申请人： H. Pogge , Roy Yu , Chandrika Prasad , Chandrasekhar Narayan
发明人： H. Pogge , Roy Yu , Chandrika Prasad , Chandrasekhar Narayan
IPC分类号： H01L23/12 , H01L21/68 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/525 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/8234 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L24/10 , H01L21/6835 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L24/13 , H01L24/81 , H01L25/0652 , H01L2224/03002 , H01L2224/0401 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/0557 , H01L2224/05572 , H01L2224/05644 , H01L2224/06181 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/17181 , H01L2224/81005 , H01L2224/94 , H01L2924/01004 , H01L2924/01006 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2224/11 , H01L2224/03 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

6. 发明授权

US06288436B1 Mixed fuse technologies 失效
标题翻译：混合保险丝技术
公开(公告)号：US06288436B1
公开(公告)日：2001-09-11
申请号：US09361960
申请日：1999-07-27
申请人： Chandrasekhar Narayan , Kenneth Arndt , Toshiaki Kirihata , David Lachtrupp , Axel Brintzinger , Gabriel Daniel
发明人： Chandrasekhar Narayan , Kenneth Arndt , Toshiaki Kirihata , David Lachtrupp , Axel Brintzinger , Gabriel Daniel
IPC分类号： H01L2900
CPC分类号： H01L22/22 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.
摘要翻译：多种不同类型的保险丝，每种类型的用于特定用途的保险丝都位于半导体集成电路晶片上，其中激活一种类型的保险丝不会使不同类型的保险丝失效。第一种类型的保险丝，例如激光激活的保险丝，主要用于修复晶圆级的缺陷，而第二种类型的保险丝，例如电激活保险丝，用于修复将IC芯片安装在模块上所发现的缺陷并在老化测试中强调模块。模块级别的缺陷通常是单电池故障，它们由电气编程的保险丝固化，以激活模块级冗余。

7. 发明授权

US6141267A Defect management engine for semiconductor memories and memory systems 有权
标题翻译：半导体存储器和存储器系统的缺陷管理引擎
公开(公告)号：US6141267A
公开(公告)日：2000-10-31
申请号：US243645
申请日：1999-02-03
申请人： Toshiaki Kirihata , Louis Lu-Chen Hsu , Chandrasekhar Narayan
发明人： Toshiaki Kirihata , Louis Lu-Chen Hsu , Chandrasekhar Narayan
IPC分类号： G11C5/02 , G11C8/06 , G11C11/00 , G11C29/00 , G11C7/00
CPC分类号： G11C29/808 , G11C11/005 , G11C29/846 , G11C5/02 , G11C8/06
摘要： A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively. The DME logic detects whether or not the redundancy address bits match or do not match the address inputs of each repair unit (self contained redundancy match detection). This couples either redundancy data bits from the DME (i.e., a matching condition) or the data bits from the domain in the memories (i.e., a no match condition) to the corresponding DQ (self-contained redundancy replacement). The DME enables an integrated redundancy means (self-contained domain selection, self-contained redundancy match detection, and self-contained redundancy replacement). Single bit replacement, multi-bit replacement, line replacement, and variable bit size replacement are discussed. Finally, an extension of the DME concept to a memory system is also discussed.
摘要翻译：用于存储器的缺陷管理引擎（DME）将多个冗余数据单元和多个冗余地址单元集成在相同的阵列中。冗余数据单元用于替换存储器中的有缺陷的单元。冗余地址单元存储有缺陷单元的地址。存储器优选地被细分为多个域。每个域中的多个缺陷单元由多个修复单元支持，每个修复单元由DME中的一个或多个冗余数据位和冗余地址位组成。当从存储器中的域读取一个或多个数据位时，DME中的相应字线同时激活耦合到字线（自包含域选择）的多个修复单元。冗余数据位和冗余地址位也分别从冗余数据单元和冗余地址单元读取。 DME逻辑检测冗余地址位是否匹配或不匹配每个修复单元的地址输入（自包含冗余匹配检测）。这将来自DME的冗余数据位（即，匹配条件）或来自存储器中的域的数据位（即，不匹配条件）耦合到相应的DQ（独立冗余替换）。 DME可实现集成的冗余手段（自包含域选择，独立冗余匹配检测和自包含冗余替换）。讨论了单位替换，多位替换，线替换和可变位大小替换。最后还讨论了将DME概念扩展到内存系统。

8. 发明授权

US5641114A Controlled temperature bonding 失效
标题翻译：受控温度键合
公开(公告)号：US5641114A
公开(公告)日：1997-06-24
申请号：US475255
申请日：1995-06-07
申请人： Raymond Robert Horton , Chandrasekhar Narayan , Michael Jon Palmer
发明人： Raymond Robert Horton , Chandrasekhar Narayan , Michael Jon Palmer
IPC分类号： B23K1/00 , B23K31/02 , B23K37/00
CPC分类号： B23K1/0016 , B23K2201/40
摘要： In a bonding station the parts of the apparatus to be bonded are retained at a thermal bias temperature at a permitted level and a thermal check valve interface is provided between the bonding location and the part of the station that would serve as a conduction heat sink, thereby thermally insulating other uninvolved parts of the structure and and confining the bonding heat to the bonding region. Such confinement reduces the dwell time that the bond must remain at the bonding temperature. The bonding station has a number of features: the parts to be bonded are maintained on a support member that is provided with a heat biasing capability that can establish the assembly at a specified temperature; a retention capability, such as the use of vacuum, is provided to maintain registration and thermal contact of the part with the support; and a thermal check valve capability is provided to control the rate of heat flow through the support member so that locallized heat is controlled in dissipation.
摘要翻译：在接合站中，要被接合的设备的部件被保持在允许的水平的热偏压温度，并且在用作传导散热器的接合位置和站的部分之间提供热止回阀接口，从而将结构的其它未掺杂部分进行绝热并且将结合热限制到接合区域。这种限制减少了粘合在粘合温度下必须保持的停留时间。粘合台具有许多特征：待粘合的部件被保持在具有可在规定温度下建立组件的热偏置能力的支撑部件上; 提供保持能力，例如使用真空，以保持部件与支撑件的配准和热接触; 并且提供热止回阀能力以控制通过支撑构件的热流的速率，从而控制局部放热的散热。

9. 发明授权

US5619357A Flat panel display containing black matrix polymer 失效
标题翻译：含黑色矩阵聚合物的平板显示器
公开(公告)号：US5619357A
公开(公告)日：1997-04-08
申请号：US466317
申请日：1995-06-06
申请人： Marie Angelopoulos , Ali Afzali-Ardakani , Claudius Feger , Chandrasekhar Narayan
发明人： Marie Angelopoulos , Ali Afzali-Ardakani , Claudius Feger , Chandrasekhar Narayan
IPC分类号： G02F1/1335
CPC分类号： G02F1/133512
摘要： A thin film transistor display that comprises a black matrix polymer layer, comprising a polymer having an optical density of at least about 0.8 per .mu.m and being self-absorbent of visible light and being selected from the group consisting of substituted and unsubstituted polyanilines, substituted and unsubstituted polyparaphenylenevinylenes, substituted and unsubstituted polythiophenes, substituted and unsubstituted polyazines, substituted and unsubstituted polyparaphenylenes, substituted and unsubstituted polyfuranes, substituted and unsubstituted polypyrroles, substituted and unsubstituted polyselenophene, substituted and unsubstituted poly-p-phenylene sulfides and substituted and unsubstituted polyacetylenes, and mixtures thereof, and copolymers thereof. The layer also comprises one or more pigments. The resistivity of the black matrix composite is 10E12 to 10E14 ohm cm.
摘要翻译：一种薄膜晶体管显示器，其包括黑矩阵聚合物层，其包含光密度为至少约0.8每μm的聚合物，并且是可吸收的可见光，并且选自取代和未取代的聚苯胺，取代的取代和未取代的聚噻吩，取代和未取代的聚噻吩，取代和未取代的聚嗪，取代和未取代的聚对苯二烯，取代和未取代的聚呋喃，取代和未取代的聚吡咯，取代和未取代的聚硒吩，取代和未取代的聚对苯硫醚和取代和未取代的聚乙炔，其混合物，及其共聚物。该层还包含一种或多种颜料。黑色矩阵复合材料的电阻率为10E12至10E14欧姆厘米。

10. 发明授权

US5471090A Electronic structures having a joining geometry providing reduced capacitive loading 失效
标题翻译：具有提供降低的电容负载的接合几何形状的电子结构
公开(公告)号：US5471090A
公开(公告)日：1995-11-28
申请号：US28023
申请日：1993-03-08
申请人： Alina Deutsch , David A. Lewis , Chandrasekhar Narayan , Anthony L. Plachy
发明人： Alina Deutsch , David A. Lewis , Chandrasekhar Narayan , Anthony L. Plachy
IPC分类号： H01L23/12 , H01L23/538 , H05K1/00 , H05K1/02 , H05K1/11 , H05K3/46 , H01L23/48 , H01L29/44
CPC分类号： H01L23/5385 , H05K1/0216 , H05K1/111 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0289 , H05K2201/0373 , H05K2201/0792 , H05K2201/0939 , H05K2201/09427 , H05K2201/10719 , H05K2203/061 , H05K3/4614 , Y02P70/611
摘要： Electrical interconnection structures are described. The electrical interconnection structures are formed by electrically interconnecting in a stack a plurality of discrete substrates. By using a plurality of discrete substrates, a multilayer dielectric/electrical conductor structure can be fabricated from individual discrete substrates each of which can be tested prior to forming a composite stack so that defects in each discrete substrate can be eliminated before inclusion into the stack. Electrical interconnection between adjacent substrate is provided by an array of contact locations on each surface of the adjacent substrates. Corresponding contacts on adjacent substrates are adapted for mutual electrical engagement. Adjacent contact locations can be thermocompression bonded. To reduce the parasitic capacitance and coupled noise between the contact pads and the electrical conductors within the interior of each discrete substrate, the contact pads on each substrate have elongated shape. The elongated contact pads or lattice pads on adjacent substrates are nonparallel and preferably orthogonal so that the corresponding pads of adjacent substrates electrically interconnect an intersecting area which varies in location along the elongated contact pads as the placement of the adjacent substrates varies in the manufacture.
摘要翻译：描述电互连结构。电互连结构通过在堆叠中电互连而形成，多个分立的衬底。通过使用多个分立的衬底，多层电介质/电导体结构可以由单独的离散衬底制成，每个离散衬底可以在形成复合堆叠之前进行测试，以便在包含在堆叠中之前可以消除每个离散衬底中的缺陷。相邻基板之间的电气互连通过相邻基板的每个表面上的接触位置阵列来提供。相邻基板上的相应触点适于相互电接合。相邻的接触位置可以热压粘合。为了减小接触焊盘和每个离散衬底内部的电导体之间的寄生电容和耦合噪声，每个衬底上的接触焊盘具有细长形状。相邻基板上的细长接触焊盘或网格焊盘是不平行的并且优选地是正交的，使得相邻衬底的相应焊盘在制造中随着相邻衬底的布置变化而沿着细长的接触焊盘将位置变化的相交区域电连接。

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