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1. 发明授权

US07521305B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07521305B2
公开(公告)日：2009-04-21
申请号：US11140952
申请日：2005-06-01
申请人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
发明人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
IPC分类号： H01L21/8234
CPC分类号： H01L21/265 , H01L21/823807 , H01L21/823842 , H01L29/78 , H01L29/7843
摘要： A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.
摘要翻译：一种制造半导体器件的方法包括以下步骤：提供形成有多个晶体管的半导体器件; 在所述半导体器件上形成具有多个层的第一应力层; 在所述半导体器件的另一表面上形成具有多个层的第二应力层; 覆盖所述第一应力层的区域上的光致抗蚀剂以覆盖所述晶体管中的至少一个; 并且对半导体器件的未被光致抗蚀剂覆盖的部分进行离子注入。在另一个实施例中，可以在离子注入之后形成第二应力层。该方法可以同时提高同一晶片上的PMOS和NMOS的器件性能。它也解决了由产生的压缩应力和拉伸应力引起的程序整合问题。

2. 发明申请

US20060160341A1 Method for fabricating semiconductor device 失效
公开(公告)号：US20060160341A1
公开(公告)日：2006-07-20
申请号：US11140952
申请日：2005-06-01
申请人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
发明人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/265 , H01L21/823807 , H01L21/823842 , H01L29/78 , H01L29/7843
摘要： A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

3. 发明授权

US07989795B2 Phase change memory device and method for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07989795B2
公开(公告)日：2011-08-02
申请号：US11857396
申请日：2007-09-18
申请人： Wei-Su Chen , Yi-Chan Chen , Hong-Hui Hsu , Chien-Min Lee , Der-Sheng Chao , Chih Wei Chen , Ming-Jinn Tsai
发明人： Wei-Su Chen , Yi-Chan Chen , Hong-Hui Hsu , Chien-Min Lee , Der-Sheng Chao , Chih Wei Chen , Ming-Jinn Tsai
IPC分类号： H01L29/04
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase change memory structure comprises a cup-shaped heating electrode on the electrode layer. An insulating layer is on the cup-shaped heating electrode along a first direction covering a portion of the cup-shaped heating electrode. An electrode structure is on the cup-shaped heating electrode along a second direction covering a portion of the insulating layer and the cup-shaped heating electrode. A pair of double spacers is on a pair of sidewalls of the electrode structure covering a portion of the cup-shaped heating electrode, wherein the double spacer comprises a phase change material spacer and an insulating material spacer on a sidewall of the phase change material spacer.
摘要翻译：提供了相变存储器件。相变存储器件包括衬底。电极层位于基板上。相变存储器结构在电极层上并电连接到电极层，其中相变存储器结构包括在电极层上的杯形加热电极。绝缘层沿着覆盖杯状加热电极的一部分的第一方向位于杯状加热电极上。电极结构沿着覆盖绝缘层和杯状加热电极的一部分的第二方向位于杯状加热电极上。一对双间隔物位于电极结构的一对侧壁上，覆盖杯状加热电极的一部分，其中双间隔物包括相变材料间隔物和在相变材料间隔物的侧壁上的绝缘材料间隔物。

4. 发明授权

US07964862B2 Phase change memory devices and methods for manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07964862B2
公开(公告)日：2011-06-21
申请号：US12056227
申请日：2008-03-26
申请人： Frederick T Chen , Yen Chuo , Hong-Hui Hsu , Jyi-Tyan Yeh , Ming-Jinn Tsai
发明人： Frederick T Chen , Yen Chuo , Hong-Hui Hsu , Jyi-Tyan Yeh , Ming-Jinn Tsai
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1691
摘要： Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.
摘要翻译：提供了相变存储器件及其制造方法。相变存储器件的示例性实施例包括设置在第一介电层中的第一电极。第二电介质层设置在第一电介质层和第一电极之上。一种相变材料层，设置在第二电介质层中以与第一电极电接触。第三电介质层设置在第二电介质层上。第二电极设置在第三电介质层中以将相变材料层和布置在第一介电层或第二介电层中的至少一个间隙电连接，从而隔离相变材料层的部分和第一或第二电介质层。

5. 发明授权

US07660147B2 Programming method for phase change memory 有权
标题翻译：相变存储器的编程方法
公开(公告)号：US07660147B2
公开(公告)日：2010-02-09
申请号：US11959108
申请日：2007-12-18
申请人： Te-Sheng Chao , Ming-Jung Chen , Philip H. Yeh , Ming-Jinn Tsai
发明人： Te-Sheng Chao , Ming-Jung Chen , Philip H. Yeh , Ming-Jinn Tsai
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.
摘要翻译：公开了一种基于非晶相和晶相之间的相变的相变存储器的编程方法。编程方法包括具有阶跃波形的电流脉冲，其向相变存储器提供第一结晶电流脉冲，并向相变存储器提供第二结晶电流脉冲。第一结晶电流脉冲具有保持第一保持时间的第一上升沿，第一下降沿和第一峰值电流。第二结晶电流脉冲具有第二峰值电流。第二峰值电流遵循第一下降沿并保持第二保持时间。

6. 发明授权

US07919768B2 Phase-change memory element 有权
标题翻译：相变存储元件
公开(公告)号：US07919768B2
公开(公告)日：2011-04-05
申请号：US12172162
申请日：2008-07-11
申请人： Frederick T Chen , Ming-Jinn Tsai
发明人： Frederick T Chen , Ming-Jinn Tsai
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L45/06 , H01L45/122 , H01L45/126 , H01L45/1273 , H01L45/1691
摘要： A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer.
摘要翻译：提出了相变存储单元。相变存储器包括底部电极; 形成为与底部电极接触的相变间隔件; 导电层，其具有垂直部分和水平部分，其中所述导电层经由所述水平部分电连接到所述相变间隔件; 以及通过导电层的垂直部分与导电层电连接的顶部电极。

7. 发明授权

US07679163B2 Phase-change memory element 有权
标题翻译：相变存储元件
公开(公告)号：US07679163B2
公开(公告)日：2010-03-16
申请号：US11748440
申请日：2007-05-14
申请人： Frederick T Chen , Ming-Jinn Tsai
发明人： Frederick T Chen , Ming-Jinn Tsai
IPC分类号： H01L29/04 , H01L29/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675
摘要： A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.
摘要翻译：公开了一种用于减少热损失的相变存储元件。相变存储元件包括复合层，其中复合层包括电介质材料和低热导率材料。在复合层内形成通孔。相变材料占据通孔的至少一部分。复合层包括交替的层或介电材料和低热导率材料的混合物。

8. 发明授权

US06309929B1 Method of forming trench MOS device and termination structure 有权
标题翻译：形成沟槽MOS器件和端接结构的方法
公开(公告)号：US06309929B1
公开(公告)日：2001-10-30
申请号：US09668906
申请日：2000-09-22
申请人： Chih-Wei Hsu , Chung-Min Liu , Ming-Che Kao , Ming-Jinn Tsai , Pu-Ju Kung
发明人： Chih-Wei Hsu , Chung-Min Liu , Ming-Che Kao , Ming-Jinn Tsai , Pu-Ju Kung
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/402 , H01L29/407 , H01L29/66348 , H01L29/7397 , H01L29/7811 , H01L29/872 , H01L29/8725
摘要： A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped. Thereafter, a termination structure oxide layer is formed through deposition, lithographic process and etching. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form the first electrode with a desired ended location and the second electrode on both side of semiconductor substrate.
摘要翻译：公开了一种同时制造沟槽MOS器件和端接结构的方法。 MOS器件可以是肖特基二极管，IGBT或DMOS，取决于制备的半导体衬底。该方法包括以下步骤：首先，在有源区中形成用于形成沟槽MOS器件的多个第一沟槽和用于形成端接结构的第二沟槽。此后，进行在所有区域上形成栅极氧化物的热氧化工艺。然后，用第一导电材料再填充第一沟槽和第二沟槽。执行蚀刻以去除多余的第一导电材料，以便在第二沟槽中形成间隔物并仅填充第一沟槽。接下来，去除栅极氧化物层。对于IGBT或DMOS器件，需要额外的热氧化和蚀刻步骤以形成导电氧化物层，而对于肖特基二极管，这两个步骤被跳过。此后，通过沉积，光刻工艺和蚀刻形成端接结构氧化物层。在背面不必要的层去除之后，依次执行溅射金属层沉积，光刻工艺和蚀刻步骤以形成具有期望的端部位置的第一电极和在半导体衬底两侧的第二电极。

9. 发明授权

US08604457B2 Phase-change memory element 有权
标题翻译：相变存储元件
公开(公告)号：US08604457B2
公开(公告)日：2013-12-10
申请号：US12269282
申请日：2008-11-12
申请人： Frederick T Chen , Ming-Jinn Tsai
发明人： Frederick T Chen , Ming-Jinn Tsai
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/1253 , H01L45/128 , H01L45/14 , H01L45/144 , H01L45/1608 , H01L45/1691
摘要： A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.
摘要翻译：提供具有电隔离导体的相变存储元件。相变存储元件包括：第一电极和第二电极; 电连接到第一电极和第二电极的相变材料层; 以及设置在第一电极和第二电极之间的至少两个电隔离导体，直接接触相变材料层。

10. 发明申请

US20090194759A1 PHASE CHANGE MEMORY DEVICE 有权
标题翻译：相变存储器件
公开(公告)号：US20090194759A1
公开(公告)日：2009-08-06
申请号：US12189087
申请日：2008-08-08
申请人： Tsung-Shune Chin , Chin-Fu Kao , Ming-Jinn Tsai , Chien-Min Lee
发明人： Tsung-Shune Chin , Chin-Fu Kao , Ming-Jinn Tsai , Chien-Min Lee
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A phase change memory device is disclosed, including a substrate, a phase change layer over the substrate, a first electrode electrically connecting a first side of the phase change layer, a second electrode electrically connecting a second side of the phase change layer, wherein the phase change layer composes mainly of gallium (Ga), antimony (Sb) and tellurium (Te) and unavoidable impurities, having the composition range of GaxTeySbz, 5
摘要翻译：公开了一种相变存储器件，包括衬底，衬底上的相变层，电连接相变层的第一侧的第一电极，电连接相变层的第二侧的第二电极，其中，相变层主要由镓（Ga），锑（Sb）和碲（Te）和不可避免的杂质构成，其组成范围为GaxTeySbz，5

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