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1. 发明申请

US20060160341A1 Method for fabricating semiconductor device 失效
公开(公告)号：US20060160341A1
公开(公告)日：2006-07-20
申请号：US11140952
申请日：2005-06-01
申请人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
发明人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/265 , H01L21/823807 , H01L21/823842 , H01L29/78 , H01L29/7843
摘要： A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

2. 发明授权

US07521305B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07521305B2
公开(公告)日：2009-04-21
申请号：US11140952
申请日：2005-06-01
申请人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
发明人： Cha-Hsin Lin , Zing-Way Pei , Ming-Jinn Tsai , Shing-Chii Lu
IPC分类号： H01L21/8234
CPC分类号： H01L21/265 , H01L21/823807 , H01L21/823842 , H01L29/78 , H01L29/7843
摘要： A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.
摘要翻译：一种制造半导体器件的方法包括以下步骤：提供形成有多个晶体管的半导体器件; 在所述半导体器件上形成具有多个层的第一应力层; 在所述半导体器件的另一表面上形成具有多个层的第二应力层; 覆盖所述第一应力层的区域上的光致抗蚀剂以覆盖所述晶体管中的至少一个; 并且对半导体器件的未被光致抗蚀剂覆盖的部分进行离子注入。在另一个实施例中，可以在离子注入之后形成第二应力层。该方法可以同时提高同一晶片上的PMOS和NMOS的器件性能。它也解决了由产生的压缩应力和拉伸应力引起的程序整合问题。

3. 发明授权

US07347228B2 Method of making semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07347228B2
公开(公告)日：2008-03-25
申请号：US11300481
申请日：2005-12-15
申请人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
发明人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
IPC分类号： H01L21/331
CPC分类号： H01L21/823807 , H01L21/31155 , H01L29/7843
摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.
摘要翻译：提供一种制造半导体器件的方法。在半导体器件的晶体管的两面上形成的高应力层用作盖层。然后通过光电阻掩模限定特定区域，并且通过离子注入改变该区域的应力。因此，在高应力层上产生压缩应力和拉伸应力。根据所公开的方法，高应力层可以同时改善在同一晶片上形成的晶体管的特性。此外，装置的载体的移动性增强。

4. 发明申请

US20060094135A1 Method of making semiconductor devices 失效
公开(公告)号：US20060094135A1
公开(公告)日：2006-05-04
申请号：US11300481
申请日：2005-12-15
申请人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
发明人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
IPC分类号： H01L21/66
CPC分类号： H01L21/823807 , H01L21/31155 , H01L29/7843
摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

5. 发明申请

US20060040479A1 Method of making semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060040479A1
公开(公告)日：2006-02-23
申请号：US11018242
申请日：2004-12-22
申请人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
发明人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
IPC分类号： H01L21/04
CPC分类号： H01L21/823807 , H01L21/31155 , H01L29/7843
摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.
摘要翻译：提供一种制造半导体器件的方法。在半导体器件的晶体管的两面上形成的高应力层用作盖层。然后通过光电阻掩模限定特定区域，并且通过离子注入改变该区域的应力。因此，在高应力层上产生压缩应力和拉伸应力。根据所公开的方法，高应力层可以同时改善在同一晶片上形成的晶体管的特性。此外，装置的载体的移动性增强。

6. 发明授权

US07033899B2 Method of making semiconductor devices 失效
公开(公告)号：US07033899B2
公开(公告)日：2006-04-25
申请号：US11018242
申请日：2004-12-22
申请人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
发明人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
IPC分类号： H01L21/8228
CPC分类号： H01L21/823807 , H01L21/31155 , H01L29/7843
摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

7. 发明授权

US07371628B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07371628B2
公开(公告)日：2008-05-13
申请号：US11228340
申请日：2005-09-19
申请人： Cha-Hsin Lin , Zing-Way Pei , Chee-Wee Liu
发明人： Cha-Hsin Lin , Zing-Way Pei , Chee-Wee Liu
IPC分类号： H01L21/336
CPC分类号： H01L21/823828 , H01L21/823807
摘要： A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.
摘要翻译：提供一种制造半导体器件的方法。该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。

8. 发明申请

US20060263959A1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060263959A1
公开(公告)日：2006-11-23
申请号：US11228340
申请日：2005-09-19
申请人： Cha-Hsin Lin , Zing-Way Pei , Chee-Wee Liu
发明人： Cha-Hsin Lin , Zing-Way Pei , Chee-Wee Liu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823828 , H01L21/823807
摘要： A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.
摘要翻译：提供一种制造半导体器件的方法。该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。

9. 发明申请

US20120133030A1 TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF 审中-公开
标题翻译： TSV基板结构及其堆叠组件
公开(公告)号：US20120133030A1
公开(公告)日：2012-05-31
申请号：US12969250
申请日：2010-12-15
申请人： Chung-Chih Wang , Pei-Jer Tzeng , Cha-Hsin Lin , Tzu-Kun Ku
发明人： Chung-Chih Wang , Pei-Jer Tzeng , Cha-Hsin Lin , Tzu-Kun Ku
IPC分类号： H01L29/41
CPC分类号： H01L21/76898 , H01L21/3212 , H01L21/32133 , H01L21/76865 , H01L21/76871 , H01L21/76883 , H01L23/481 , H01L23/5384 , H01L23/562 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H01L2224/13009 , H01L2224/13023 , H01L2224/16 , H01L2224/16146 , H01L2224/81 , H01L2224/8114 , H01L2224/81911 , H01L2225/06541 , H01L2924/00014 , H01L2224/05552
摘要： The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.
摘要翻译：本公开提供TSV衬底结构和多个衬底结构的层叠组件，TSV衬底结构包括：衬底，其包括第一表面，相应的第二表面以及将第一表面与第二表面通过第二表面连通的TSV 基质; 以及完全填充TSV的导体单元，所述导体单元包括分别具有对应于所述基板的第一和第二表面的第一和第二端的导体本体。

10. 发明申请

US20100164062A1 METHOD OF MANUFACTURING THROUGH-SILICON-VIA AND THROUGH-SILICON-VIA STRUCTURE 审中-公开
标题翻译：通过硅晶体和通过硅结构制造方法
公开(公告)号：US20100164062A1
公开(公告)日：2010-07-01
申请号：US12480694
申请日：2009-06-09
申请人： Ching-Chiun Wang , Tai-Yuan Wu , Yu-Sheng Chen , Cha-Hsin Lin
发明人： Ching-Chiun Wang , Tai-Yuan Wu , Yu-Sheng Chen , Cha-Hsin Lin
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L27/0629 , H01L2224/05001 , H01L2224/05009 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/056 , H01L2224/05647 , H01L2224/05684 , H01L2224/13022 , H01L2224/13025 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13157 , H01L2924/00014 , H01L2924/0105 , H01L2924/013
摘要： A method of manufacturing through-silicon-via (TSV) and a TSV structure are provided. The TSV structure includes a silicon substrate, an annular capacitor, a conductive through-via, a layer of low-k material, and a bump. The annular capacitor is within the silicon substrate and constituted of a first conductive layer, a capacitor dielectric layer, and a second conductive layer from the inside to the outside. The conductive through-via is disposed in the silicon substrate surrounded by the annular capacitor, and the layer of low-k material is between the annular capacitor and the conductive through-via. The bump is in touch with the conductive through-via for bonding other chip.
摘要翻译：提供了通过硅通孔（TSV）和TSV结构的方法。 TSV结构包括硅衬底，环形电容器，导电通孔，低k材料层和凸块。环形电容器在硅衬底内，由第一导电层，电容器电介质层和从内向外的第二导电层构成。导电通孔设置在由环形电容器包围的硅衬底中，低k材料层位于环形电容器和导电通孔之间。凸块与用于粘合其他芯片的导电通孔相接触。

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