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1. 发明授权

US07056830B2 Method for plasma etching a dielectric layer 失效
标题翻译：等离子体蚀刻电介质层的方法
公开(公告)号：US07056830B2
公开(公告)日：2006-06-06
申请号：US10655231
申请日：2003-09-03
申请人： Walter R. Merry , Cecilia Y. Mak , Kam S. Law
发明人： Walter R. Merry , Cecilia Y. Mak , Kam S. Law
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/30655 , H01L21/31116
摘要： A method of etching a dielectric layer formed on a substrate including a sequence of processing cycles, wherein each cycle comprises steps of depositing an inactive polymeric film, activating the film to etch the structure, and removing the film is disclosed. In one embodiment, the method uses a fluorocarbon gas to form the polymeric film and a substrate bias to activate such film.
摘要翻译：一种蚀刻在衬底上形成的包括一系列处理循环的电介质层的方法，其中每个循环包括沉积非活性聚合物膜，激活该膜以蚀刻该结构并除去该膜的步骤。在一个实施方案中，该方法使用碳氟化合物气体来形成聚合物膜和衬底偏压以激活这种膜。

2. 发明授权

US07220685B2 Method for depositing porous films 有权
标题翻译：沉积多孔膜的方法
公开(公告)号：US07220685B2
公开(公告)日：2007-05-22
申请号：US11483034
申请日：2006-07-07
申请人： Cecilia Y. Mak , Kam S. Law
发明人： Cecilia Y. Mak , Kam S. Law
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/3124 , H01L21/31625 , H01L21/31629 , H01L21/31695 , H01L2221/1047
摘要： A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon from the codeposit to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. After codeposition, the codeposit is exposed to a selective silicon removal reagent that can preferentially remove the silicon in the codeposit, leaving behind a porous structure. Repeated execution of the codeposition and the selective silicon removal steps build up thickness of the porous film. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The general method is also advantageous for forming other porous films for other applications.
摘要翻译：提供了一种用于沉积多孔二氧化硅和掺杂二氧化硅膜的方法。该方法使用循环方案，其中每个循环包括首先将二氧化硅与硅共沉积，然后从共沉积物中选择性除去硅以形成多孔结构。在优选的实施方案中，共沉积通过等离子体增强化学气相沉积进行。共沉积后，共沉积物暴露于选择性硅去除剂，其可优先除去共沉积物中的硅，留下多孔结构。重复执行共沉积和选择性硅去除步骤建立了多孔膜的厚度。使用该方法可以获得具有高度均匀的小孔和所需孔隙率分布的多孔膜。该方法有利于形成用于半导体集成电路制造的宽范围的低k电介质。一般方法对于形成用于其它应用的其它多孔膜也是有利的。

3. 发明授权

US07132374B2 Method for depositing porous films 有权
标题翻译：沉积多孔膜的方法
公开(公告)号：US07132374B2
公开(公告)日：2006-11-07
申请号：US10920602
申请日：2004-08-17
申请人： Cecilia Y. Mak , Kam S. Law
发明人： Cecilia Y. Mak , Kam S. Law
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/3124 , H01L21/31625 , H01L21/31629 , H01L21/31695 , H01L2221/1047
摘要： A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. The reagent feed stream comprises a mixture of codeposition reagents and a selective silicon removal reagent. RF power modulation is used to control the codeposition and the selective silicon removal steps with the later proceeds whenever the RF power is turned off or reduced to a low level. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The method is also advantageous for forming other porous films for other applications.
摘要翻译：提供了一种用于沉积多孔二氧化硅和掺杂二氧化硅膜的方法。该方法使用循环方案，其中每个循环包括首先将二氧化硅与硅共沉积，然后选择性地除去硅以形成多孔结构。在优选的实施方案中，共沉积通过等离子体增强化学气相沉积进行。试剂进料流包含共沉积试剂和选择性硅去除试剂的混合物。 RF功率调制用于控制共沉积和选择性硅去除步骤，随着RF功率关闭或降低到低电平，随后进行。使用该方法可以获得具有高度均匀的小孔和所需孔隙率分布的多孔膜。该方法有利于形成用于半导体集成电路制造的宽范围的低k电介质。该方法对于形成用于其它应用的其它多孔膜也是有利的。

4. 发明授权

US07087179B2 Optical integrated circuits (ICs) 有权
标题翻译：光集成电路（IC）
公开(公告)号：US07087179B2
公开(公告)日：2006-08-08
申请号：US09734950
申请日：2000-12-11
申请人： Cecilia Y. Mak , John M. White , Kam S. Law , Dan Maydan
发明人： Cecilia Y. Mak , John M. White , Kam S. Law , Dan Maydan
IPC分类号： B29D11/00
CPC分类号： G02B6/12004 , G02B6/13 , G02B6/132
摘要： In one aspect, the invention provides methods and apparatus for forming optical devices on large area substrates. The large area substrates are preferably made of quartz, silica or fused silica. The large area substrates enable larger optical devices to be formed on a single die. In another aspect, the invention provides methods and apparatus for forming integrated optical devices on large area substrates, such as quartz, silica or fused silica substrates. In another aspect, the invention provides methods and apparatus for forming optical devices using damascene techniques on large area substrates or silicon substrates. In another aspect, methods for forming optical devices by bonding an upper cladding layer on a lower cladding and a core is provided.
摘要翻译：一方面，本发明提供了用于在大面积基板上形成光学装置的方法和装置。大面积基板优选由石英，二氧化硅或熔融二氧化硅制成。大面积基板使得能够在单个管芯上形成更大的光学器件。另一方面，本发明提供了用于在大面积衬底（例如石英，二氧化硅或熔融二氧化硅衬底）上形成集成光学器件的方法和装置。在另一方面，本发明提供了使用大面积衬底或硅衬底上的镶嵌技术形成光学器件的方法和装置。在另一方面，提供了通过将下包层和芯上的上包层结合来形成光器件的方法。

5. 发明授权

US08444364B2 Auto-sequencing multi-directional inline processing apparatus 有权
标题翻译：自动排序多向在线处理设备
公开(公告)号：US08444364B2
公开(公告)日：2013-05-21
申请号：US12965798
申请日：2010-12-10
申请人： Wendell Thomas Blonigan , Masato Toshima , Kam S. Law , David Eric Berkstresser , Steve Kleinke , Craig Lyle Stevens
发明人： Wendell Thomas Blonigan , Masato Toshima , Kam S. Law , David Eric Berkstresser , Steve Kleinke , Craig Lyle Stevens
IPC分类号： B65G53/46
CPC分类号： H01L21/67745 , C23C16/45565 , G06T7/0004 , H01J37/32733 , H01L21/67173 , H01L21/67739 , H01L21/67748 , H01L21/67754 , Y10T29/49948
摘要： An apparatus and method for concurrent processing of several substrates. The system employs a novel architecture which, while being linear, may autonomously sequence processing and move substrates in different directions as necessary. The system moves several substrates concurrently; however, unlike the prior art it does not utilize trays.
摘要翻译：一种并行处理多个基板的装置和方法。该系统采用一种新颖的架构，其在线性的情况下可以根据需要自主地对处理进行顺序处理和移动基板。系统同时移动多个基板; 然而，与现有技术不同，它不利用托盘。

6. 发明授权

US06610354B2 Plasma display panel with a low k dielectric layer 失效
公开(公告)号：US06610354B2
公开(公告)日：2003-08-26
申请号：US09886174
申请日：2001-06-18
申请人： Kam S. Law , Quanyuan Shang , Takako Takehara , Taekyung Won , William R. Harshbarger , Dan Maydan
发明人： Kam S. Law , Quanyuan Shang , Takako Takehara , Taekyung Won , William R. Harshbarger , Dan Maydan
IPC分类号： C23C1640
CPC分类号： H01J11/38 , H01J11/12
摘要： A plasma display panel including a low k dielectric layer. In one embodiment, the dielectric layer is comprises a fluorine-doped silicon oxide layer such as an SiOF layer. In another embodiment, the dielectric layer comprises a Black Diamond™ layer. In certain embodiments, a capping layer such as SiN or SiON is deposited over the dielectric layer.

7. 发明授权

US06451390B1 Deposition of TEOS oxide using pulsed RF plasma 有权
公开(公告)号：US06451390B1
公开(公告)日：2002-09-17
申请号：US09544728
申请日：2000-04-06
申请人： Haruhiro H. Goto , Takako Takehara , Carl A. Sorensen , William R. Harshbarger , Kam S. Law
发明人： Haruhiro H. Goto , Takako Takehara , Carl A. Sorensen , William R. Harshbarger , Kam S. Law
IPC分类号： H05H124
CPC分类号： C03C17/245 , C03C2217/213 , C03C2218/153
摘要： A method for the deposition of a silicon dioxide film onto a substrate using plasma enhanced chemical vapor deposition and TEOS is disclosed. The method includes controlling the deposition rate of silicon dioxide on a substrate by pulsing the radio frequency power supply used to generate a TEOS oxide plasma. The obtained silicon dioxide film is good in electrical and mechanical film properties for the application of forming thin film transistors.

8. 发明授权

US6055927A Apparatus and method for white powder reduction in silicon nitride deposition using remote plasma source cleaning technology 失效
公开(公告)号：US6055927A
公开(公告)日：2000-05-02
申请号：US782169
申请日：1997-01-14
申请人： Quanyuan Shang , Robert McCormick Robertson , Kam S. Law , Dan Maydan
发明人： Quanyuan Shang , Robert McCormick Robertson , Kam S. Law , Dan Maydan
IPC分类号： B08B7/00 , C23C16/42 , C23C16/44 , C23C16/52 , H01L21/205 , H01L21/3065 , H01L21/31 , C23C16/00
CPC分类号： C23C16/4405
摘要： An apparatus and method for reducing the production of white powder in a process chamber used for depositing silicon nitride. Steps of the method include heating at least a portion of a wall of the process chamber; providing a liner covering a substantial portion of a wall of the process chamber; providing a remote chamber connected to the interior of the process chamber; causing a plasma of cleaning gas in the remote chamber; and flowing a portion of the plasma of cleaning gas into the process chamber. The apparatus includes a deposition chamber having walls; means for heating the walls, the means thermally coupled to the walls; a liner covering a substantial portion of the walls; a remote chamber disposed outside of the chamber; an activation source adapted to deliver energy into the remote chamber; a first conduit for flowing a precursor gas from a remote gas supply into the remote chamber where it is activated by the activation source to form a reactive species; and a second conduit for flowing the reactive species from the remote chamber into the deposition chamber.

9. 发明授权

US5204288A Method for planarizing an integrated circuit structure using low melting inorganic material 失效
标题翻译：使用低熔点无机材料平面化集成电路结构的方法
公开(公告)号：US5204288A
公开(公告)日：1993-04-20
申请号：US845544
申请日：1992-03-04
申请人： Jeffrey Marks , Kam S. Law , David N. Wang , Dan Maydan
发明人： Jeffrey Marks , Kam S. Law , David N. Wang , Dan Maydan
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/31
CPC分类号： H01L21/3105 , H01L21/31055 , H01L21/31604 , H01L21/76819 , H01L23/3157 , H01L2924/0002 , Y10S148/133 , Y10S438/913
摘要： A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus. In a particularly preferred embodiment, all of the steps are carried out in the same chamber of the apparatus. An additional etching step may be carried out after depositing the first insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.
摘要翻译：公开了使用低熔点无机平面化材料来平坦化CVD装置中的集成电路结构的平面化工艺，该无机平面化材料包括使诸如氧化硼玻璃之类的低熔点无机平面化层在诸如氧化物硅，然后干法蚀刻低熔点无机平面化层以使结构平坦化，然后沉积另外的绝缘材料层以封装可能是吸湿性的低熔点玻璃平坦化层的任何剩余部分。该方法消除了对通常在真空装置外进行的有机基平坦化层的应用的独立涂布，干燥和固化步骤的需要。在优选实施例中，沉积步骤和蚀刻步骤全部进行而不从集成电路结构从设备中移除。在特别优选的实施例中，所有步骤在装置的相同腔室中进行。在沉积第一绝缘层之后并且在沉积平坦化层以去除在绝缘层中形成的任何空隙之前，可以进行另外的蚀刻步骤。

10. 发明授权

US4960488A Reactor chamber self-cleaning process 失效
标题翻译：反应室自清洁过程
公开(公告)号：US4960488A
公开(公告)日：1990-10-02
申请号：US455799
申请日：1989-12-19
申请人： Kam S. Law , Cissy Leung , Ching C. Tang , Kenneth S. Collins , Mei Chang , Jerry Y. K. Wong , David Nin-Kou Wang
发明人： Kam S. Law , Cissy Leung , Ching C. Tang , Kenneth S. Collins , Mei Chang , Jerry Y. K. Wong , David Nin-Kou Wang
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/44 , C23C16/4405 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01J37/32862 , H01L21/31604 , Y02C20/30 , Y02P70/605 , Y10S438/905
摘要： A process for cleaning a reactor chamber both locally adjacent the RF electrodes and also throughout the chamber and the exhaust system to the including components such as the throttle valve. Preferably, a two-step continuous etch sequence is used in which the first step uses relatively high pressure, close electrode spacing and fluorocarbon gas chemistry for etching the electodes locally and the second step uses relatively lower pressure, farther electrode spacing and fluorinated gas chemistry for etching throughout the chamber and exhaust system. The local and extended etch steps may be used separately as well as together.
摘要翻译：用于清洁反射室的方法，所述反应室局部地邻近RF电极以及整个室和排气系统到包括诸如节流阀的部件。优选地，使用两步连续蚀刻序列，其中第一步骤使用相对高的压力，紧密的电极间距和碳氟化合物气体化学物质来局部蚀刻电极，并且第二步骤使用相对较低的压力，更远的电极间距和氟化气体化学蚀刻整个腔室和排气系统。本地和延长的蚀刻步骤可以单独使用和一起使用。

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