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1. 发明申请

US20050154948A1 Accelerated scan circuitry and method for reducing scan test data volume and execution time 有权
标题翻译：加速扫描电路和减少扫描测试数据量和执行时间的方法
公开(公告)号：US20050154948A1
公开(公告)日：2005-07-14
申请号：US10931191
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence Cooke
发明人： Bulent Dervisoglu , Laurence Cooke
IPC分类号： G01R31/3183 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
摘要翻译：描述了使用组合函数测试数据压缩的架构和方法，以提供扫描链的连续段之间的串行耦合。压缩序列扫描序列从识别所需Care_In值的扫描状态开始，并迭代地使用符号计算，以便确定必需的先前扫描链状态，直到计算的先前扫描链状态与给定的已知起始扫描链状态相匹配为止。还提出了一种新型触发器的新颖设计，允许实现可以轻松启动和停止的扫描链，而不需要额外的控制信号。讨论了架构和方法的扩展以处理扫描链中的未知（X）值，将压缩数据适当地计时到多个扫描链中，使用数据扩展网络以及使用伪随机信号发生器提供分段扫描链，以实施内置自检（BIST）。

2. 发明申请

US20050028060A1 Accelerated scan circuitry and method for reducing scan test data volume and execution time 失效
公开(公告)号：US20050028060A1
公开(公告)日：2005-02-03
申请号：US10931079
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence Cooke
发明人： Bulent Dervisoglu , Laurence Cooke
IPC分类号： G01R31/3183 , G01R31/3185 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

3. 发明申请

US20070162803A1 Accelerated Scan Circuitry and Method for Reducing Scan Test Data Volume and Execution Time 有权
标题翻译：加速扫描电路和减少扫描测试数据量和执行时间的方法
公开(公告)号：US20070162803A1
公开(公告)日：2007-07-12
申请号：US11680684
申请日：2007-03-01
申请人： Bulent Dervisoglu , Laurence Cooke
发明人： Bulent Dervisoglu , Laurence Cooke
IPC分类号： G01R31/28
CPC分类号： G01R31/318385 , G01R31/318335 , G01R31/318536 , G01R31/318547 , G01R31/318552 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
摘要翻译：描述了使用组合函数测试数据压缩的架构和方法，以提供扫描链的连续段之间的串行耦合。压缩序列扫描序列从识别所需Care_In值的扫描状态开始，并迭代地使用符号计算，以便确定必需的先前扫描链状态，直到计算的先前扫描链状态与给定的已知起始扫描链状态相匹配为止。还提出了一种新型触发器的新颖设计，允许实现可以轻松启动和停止的扫描链，而无需额外的控制信号。讨论了架构和方法的扩展以处理扫描链中的未知（X）值，将压缩数据适当地计时到多个扫描链中，使用数据扩展网络以及使用伪随机信号发生器提供分段扫描链，以实施内置自检（BIST）。

4. 发明申请

US20060064615A1 On-chip service processor 无效
公开(公告)号：US20060064615A1
公开(公告)日：2006-03-23
申请号：US11261762
申请日：2005-10-31
申请人： Bulent Dervisoglu , Laurence Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence Cooke , Vacit Arat
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

5. 发明申请

US20060195746A1 Variable clocked scan test improvements 失效
标题翻译：可变时钟扫描测试改进
公开(公告)号：US20060195746A1
公开(公告)日：2006-08-31
申请号：US11182809
申请日：2005-07-18
申请人： Laurence Cooke , Bulent Dervisoglu
发明人： Laurence Cooke , Bulent Dervisoglu
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318552
摘要： Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
摘要翻译：添加特定的测试逻辑可以提高从现有的可变扫描测试逻辑实现的测试向量压缩的水平。可以使用给定期望的未压缩向量值来确定压缩向量状态的方法，并且还可以使用用于通过将适当的代码或代码插入到芯片中来选择性地启用芯片上的测试或其他特征的技术。技术可以用于将各种类型的复位操作并入并应用于多个可变扫描测试逻辑串，作为使测试向量压缩计算时间最小化的方法。

6. 发明申请

US20070226455A1 Variable clocked heterogeneous serial array processor 审中-公开
标题翻译：可变时钟异构串行数组处理器
公开(公告)号：US20070226455A1
公开(公告)日：2007-09-27
申请号：US11374790
申请日：2006-03-13
申请人： Laurence Cooke
发明人： Laurence Cooke
IPC分类号： G06F15/00
CPC分类号： G06F15/7867 , G06F7/504 , G06F7/5275 , G06F7/57 , G06F9/30014 , G06F15/8015
摘要： A serial array processor, whose execution unit, which s comprised of a multiplicity of single bit arithmetic logic units (ALUs), performs parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while the instruction unit is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit, is presented. This architecture utilizes combinations of masked address decodes to program registers which control the routing of data from memory, to the ALUs and back to memory. In addition the processor has extensions for calculating or measuring and adjusting the execution unit's clock to match the time required to execute each serial clock cycle of any particular operation, as well as techniques specific to this architecture for preprocessing multiple instructions following a branch, to provide a “branch look-ahead” capability.
摘要翻译：由多个单比特算术逻辑单元（ALU）组成的执行单元的串行阵列处理器通过串行地访问和处理存储器中的所有字的子集执行并行操作，一次一位，当指令单元预取下一条指令时，呈现与执行单元正交的方式一次一个字。该架构使用掩蔽地址解码的组合来编程寄存器，其控制数据从存储器到ALU以及返回存储器的路由。此外，处理器具有用于计算或测量和调整执行单元的时钟的扩展，以匹配执行任何特定操作的每个串行时钟周期所需的时间，以及用于预处理分支之后的多个指令的该架构特有的技术，以提供 “分支预先”能力。

7. 发明授权

US07463062B2 Structured integrated circuit device 有权
标题翻译：结构化集成电路器件
公开(公告)号：US07463062B2
公开(公告)日：2008-12-09
申请号：US11739538
申请日：2007-04-24
申请人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
发明人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H01L2224/14 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H03K19/17728 , H03K19/1774 , H03K19/17796
摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.
摘要翻译：可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中定制可能都在单个通孔层上完成。

8. 发明申请

US20070187808A1 Customizable power and ground pins 审中-公开
标题翻译：可定制的电源和接地引脚
公开(公告)号：US20070187808A1
公开(公告)日：2007-08-16
申请号：US11354957
申请日：2006-02-16
申请人： Stan Mihelcic , Adam Levinthal , Laurence Cooke
发明人： Stan Mihelcic , Adam Levinthal , Laurence Cooke
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/49109 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01057 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/1517 , H01L2924/15312 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： A configurable logic array composed of: a multiplicity of logic cells, each containing look-up tables, a multiplicity of customizable I/O cells, each containing a multiplicity of pads; and a customizable via connection layer for customizing the cells and interconnect between them, may be constructed to include the option of customizing the I/O cells to act as power or ground pins. Assigning custom power and ground pins may depend on the types of I/O cells and package bonding options.
摘要翻译：一个可配置的逻辑阵列，由以下组成：多个逻辑单元，每个包含查找表，多个可定制I / O单元，每个单元包含多个焊盘; 并且可以构造用于定制单元和它们之间的互连的可定制的通孔连接层，以包括定制I / O单元以用作电源或接地引脚的选项。分配定制电源和接地引脚可能取决于I / O单元的类型和封装绑定选项。

9. 发明申请

US20070168798A1 Scan string segmentation for digital test compression 失效
标题翻译：扫描字符串分割用于数字测试压缩
公开(公告)号：US20070168798A1
公开(公告)日：2007-07-19
申请号：US11208883
申请日：2005-08-23
申请人： Laurence Cooke
发明人： Laurence Cooke
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A new technique to determine the placement of exclusive-ors in each scan string of a chip may be used to achieve improved test vector compression, and this may be used along with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan string reordering, and to minimize the test vector compression computation time.
摘要翻译：用于确定芯片的每个扫描串中的排他位置的新技术可以用于实现改进的测试向量压缩，并且这可以与方法一起使用以最小化异或逻辑的开销来消除时钟启用多个扫描字符串的逻辑，以最小化现有测试逻辑插入和扫描字符串重新排序的更改，并最大限度地减少测试向量压缩计算时间。

10. 发明申请

US20070188188A1 Structured Integrated Circuit Device 有权
标题翻译：结构化集成电路器件
公开(公告)号：US20070188188A1
公开(公告)日：2007-08-16
申请号：US11739538
申请日：2007-04-24
申请人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
发明人： Zvi Or-Bach , Ze'ev Wurman , Adam Levinthal , Laurence Cooke , Stan Mihelcic
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H01L2224/14 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311 , H03K19/17728 , H03K19/1774 , H03K19/17796
摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.
摘要翻译：可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中定制可能都在单个通孔层上完成。

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