专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06687865B1 On-chip service processor for test and debug of integrated circuits 有权
标题翻译：用于集成电路测试和调试的片上服务处理器
公开(公告)号：US06687865B1
公开(公告)日：2004-02-03
申请号：US09275726
申请日：1999-03-24
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R3128
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含片上逻辑分析仪，用于捕获用户可定义电路中的逻辑状态序列。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

2. 发明申请

US20080168309A1 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US20080168309A1
公开(公告)日：2008-07-10
申请号：US11424610
申请日：2006-06-16
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G06F11/00
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

3. 发明授权

US07200784B2 Accelerated scan circuitry and method for reducing scan test data volume and execution time 有权
公开(公告)号：US07200784B2
公开(公告)日：2007-04-03
申请号：US10931191
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

4. 发明授权

US07197681B2 Accelerated scan circuitry and method for reducing scan test data volume and execution time 失效
标题翻译：加速扫描电路和减少扫描测试数据量和执行时间的方法
公开(公告)号：US07197681B2
公开(公告)日：2007-03-27
申请号：US10750949
申请日：2004-01-05
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G01R31/28
CPC分类号： G01R31/318385 , G01R31/318335 , G01R31/318536 , G01R31/318547 , G01R31/318552 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
摘要翻译：描述了使用组合函数测试数据压缩的架构和方法，以提供扫描链的连续段之间的串行耦合。压缩序列扫描序列从识别所需Care_In值的扫描状态开始，并迭代地使用符号计算，以便确定必需的先前扫描链状态，直到计算的先前扫描链状态与给定的已知起始扫描链状态相匹配为止。还提出了一种新型触发器的新颖设计，允许实现可以轻松启动和停止的扫描链，而无需额外的控制信号。讨论了架构和方法的扩展以处理扫描链中的未知（X）值，将压缩数据适当地计时到多个扫描链中，使用数据扩展网络以及使用伪随机信号发生器提供分段扫描链，以实施内置自检（BIST）。

5. 发明授权

US06816996B2 Hierarchical test circuit structure for chips with multiple circuit blocks 有权
公开(公告)号：US06816996B2
公开(公告)日：2004-11-09
申请号：US10327369
申请日：2002-12-20
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G06F1750
摘要： A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical. An existing boundary scan may be easily modified for use in the hierarchical structure by adding push instructions to send it to a lower-level test circuit block, and pop instructions to return control to the higher level test circuit block.

6. 发明申请

US20100162046A1 ON-CHIP SERVICE PROCESSOR 有权
标题翻译：在线服务处理器
公开(公告)号：US20100162046A1
公开(公告)日：2010-06-24
申请号：US12717391
申请日：2010-03-04
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G06F11/26
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

7. 发明授权

US07188286B2 Accelerated scan circuitry and method for reducing scan test data volume and execution time 失效
公开(公告)号：US07188286B2
公开(公告)日：2007-03-06
申请号：US10931079
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

8. 发明申请

US20050154948A1 Accelerated scan circuitry and method for reducing scan test data volume and execution time 有权
标题翻译：加速扫描电路和减少扫描测试数据量和执行时间的方法
公开(公告)号：US20050154948A1
公开(公告)日：2005-07-14
申请号：US10931191
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence Cooke
发明人： Bulent Dervisoglu , Laurence Cooke
IPC分类号： G01R31/3183 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
摘要翻译：描述了使用组合函数测试数据压缩的架构和方法，以提供扫描链的连续段之间的串行耦合。压缩序列扫描序列从识别所需Care_In值的扫描状态开始，并迭代地使用符号计算，以便确定必需的先前扫描链状态，直到计算的先前扫描链状态与给定的已知起始扫描链状态相匹配为止。还提出了一种新型触发器的新颖设计，允许实现可以轻松启动和停止的扫描链，而不需要额外的控制信号。讨论了架构和方法的扩展以处理扫描链中的未知（X）值，将压缩数据适当地计时到多个扫描链中，使用数据扩展网络以及使用伪随机信号发生器提供分段扫描链，以实施内置自检（BIST）。

9. 发明授权

US06886121B2 Hierarchical test circuit structure for chips with multiple circuit blocks 有权
标题翻译：具有多个电路块的芯片的分层测试电路结构
公开(公告)号：US06886121B2
公开(公告)日：2005-04-26
申请号：US09765958
申请日：2001-01-18
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/822 , H01L27/04 , G06F17/50
CPC分类号： G01R31/318505 , G01R31/318536
摘要： A hierarchical test control network for an integrated circuit includes a top-level test control circuit block having a chip access port (CAP) controller. The hierarchical test control network also has multiple lower-level test control circuit blocks connected to the top-level test control circuit block in a hierarchical structure. Each of the lower-level test control circuit blocks are a socket access port (SAP) controller. Test operation is transferred downward and upwards within said hierarchical structure.
摘要翻译：用于集成电路的分级测试控制网络包括具有芯片接入端口（CAP）控制器的顶级测试控制电路块。分级测试控制网络还具有以分层结构连接到顶级测试控制电路块的多个下级测试控制电路块。每个下级测试控制电路块都是一个套接字接入端口（SAP）控制器。测试操作在所述分级结构内向下或向下传送。

10. 发明申请

US20050028060A1 Accelerated scan circuitry and method for reducing scan test data volume and execution time 失效
公开(公告)号：US20050028060A1
公开(公告)日：2005-02-03
申请号：US10931079
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence Cooke
发明人： Bulent Dervisoglu , Laurence Cooke
IPC分类号： G01R31/3183 , G01R31/3185 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式