会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Electrochemical fabrication method including elastic joining of structures
    • 包括结构弹性连接的电化学制造方法
    • US08070931B1
    • 2011-12-06
    • US12345624
    • 2008-12-29
    • Adam L. CohenVacit AratMichael S. LockardDennis R. Smalley
    • Adam L. CohenVacit AratMichael S. LockardDennis R. Smalley
    • C25D5/02
    • B29C65/56B33Y10/00C25D5/02Y10T29/49885
    • Embodiments are directed to methods for forming multi-layer three-dimensional structures involving the joining of at least two structural elements, at least one of which is formed as a multi-layer three-dimensional structure, wherein the joining occurs via one of: (1) elastic deformation and elastic recovery and subsequent retention of elements relative to each other, (2) relative deformation of an initial portion of at least one element relative to another portion of the at least one element until the at least two elements are in a desired retention position after which the deformation is reduced or eliminated and a portion of at least one element is brought into position which in turn locks the at least two elements together via contact with one another including contact with the initial portion of at least one element, or (3) moving a retention region of one element into the retention region of the other element, without deformation of either element, along a path including a loading region of the other element and wherein during normal use the first and second elements are configured relative to one another so that the loading region of the second elements is not accessible to the retention region of the first element.
    • 实施例涉及用于形成多层三维结构的方法,所述多层三维结构涉及至少两个结构元件的接合,其中至少一个结构元件形成为多层三维结构,其中通过以下之一进行接合:( 1)弹性变形和弹性恢复以及随后元件相对于彼此的保留,(2)至少一个元件的初始部分相对于至少一个元件的另一部分的相对变形,直到至少两个元件处于 期望的保持位置,在此之后,变形被减小或消除,并且至少一个元件的一部分进入位置,其又通过彼此接触将至少两个元件锁定在一起,包括与至少一个元件的初始部分的接触, 或(3)将一个元件的保持区域移动到另一个元件的保持区域中,而不会使任一元件变形,沿着包括装载物 g区域,并且其中在正常使用期间,第一和第二元件相对于彼此构造,使得第二元件的加载区域不能被第一元件的保持区域访问。
    • 10. 发明申请
    • On-chip service processor
    • 片上服务处理器
    • US20080168309A1
    • 2008-07-10
    • US11424610
    • 2006-06-16
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G06F11/00
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。