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    • 2. 发明申请
    • On-chip service processor
    • 片上服务处理器
    • US20080168309A1
    • 2008-07-10
    • US11424610
    • 2006-06-16
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G06F11/00
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。
    • 3. 发明授权
    • On-chip service processor for test and debug of integrated circuits
    • 用于集成电路测试和调试的片上服务处理器
    • US06687865B1
    • 2004-02-03
    • US09275726
    • 1999-03-24
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G01R3128
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含片上逻辑分析仪,用于捕获用户可定义电路中的逻辑状态序列。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。
    • 4. 发明申请
    • ON-CHIP SERVICE PROCESSOR
    • 在线服务处理器
    • US20100162046A1
    • 2010-06-24
    • US12717391
    • 2010-03-04
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G06F11/26
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。
    • 5. 发明授权
    • On-chip service processor
    • 片上服务处理器
    • US08996938B2
    • 2015-03-31
    • US13027009
    • 2011-02-14
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G01R31/28G01R31/3185G01R31/317G01R31/3183
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。
    • 6. 发明申请
    • ON-CHIP SERVICE PROCESSOR
    • 在线服务处理器
    • US20120011411A1
    • 2012-01-12
    • US13027009
    • 2011-02-14
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G01R31/3177G06F11/25
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。
    • 7. 发明授权
    • On-chip service processor
    • 片上服务处理器
    • US07836371B2
    • 2010-11-16
    • US11424610
    • 2006-06-16
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G01R31/28
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。
    • 9. 发明授权
    • On-chip service processor
    • 片上服务处理器
    • US06964001B2
    • 2005-11-08
    • US10767265
    • 2004-01-30
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • Bulent DervisogluLaurence H. CookeVacit Arat
    • G01R31/317G01R31/3185G01R31/28
    • G01R31/318572G01R31/31705G01R31/31723G01R31/318385G01R31/318566
    • An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    • 描述了一种集成电路,其包括存储的程序处理器,用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。 外部接口可以通过现有的测试接口或单独的串行或并行端口。 测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串,或用于向用户定义的逻辑提供伪随机位序列。 测试和调试电路还可以包含片上逻辑分析仪,用于捕获用户可定义电路中的逻辑状态序列。 测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。