专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06490717B1 Generation of sub-netlists for use in incremental compilation 有权
标题翻译：生成用于增量编译的子网表
公开(公告)号：US06490717B1
公开(公告)日：2002-12-03
申请号：US09639657
申请日：2000-08-15
申请人： Bruce Pedersen , Francis B. Heile , Marwan Adel Khalaf , David Wolk Mendel
发明人： Bruce Pedersen , Francis B. Heile , Marwan Adel Khalaf , David Wolk Mendel
IPC分类号： G06F1750
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F8/65 , G06F8/71 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F2217/04 , G06Q10/06 , G06Q10/10 , Y10S707/99953 , Y10S707/99954
摘要： A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a “sub-netlist” within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.
摘要翻译：公开了一种用于执行先前编译然后由设计者改变的电子设计的增量重新编译的技术。这是通过在更改的设计的较大网表中识别“子网表”来实现的。子网表包含设计师对原始设计的变化的影响范围。在增量重新编译期间，仅编制子网表; 网表的剩余部分与以前的编译一样。子网表合成后，从以前的编译中集成回合成的网表。用于改变后的设计的新合成的网表被映射到逻辑单元，然后将其合并到目标硬件设备上。

2. 发明授权

US6134705A Generation of sub-netlists for use in incremental compilation 失效
公开(公告)号：US6134705A
公开(公告)日：2000-10-17
申请号：US958002
申请日：1997-10-27
申请人： Bruce Pedersen , Francis B. Heile , Marwan Adel Khalaf , David Wolk Mendel
发明人： Bruce Pedersen , Francis B. Heile , Marwan Adel Khalaf , David Wolk Mendel
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185 , G06F9/44 , G06F9/445 , G06F11/14 , G06F11/273 , G06F11/28 , G06F12/00 , G06F17/50 , G06Q10/06 , G06Q10/10 , H01L21/82
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F8/65 , G06F8/71 , G06Q10/06 , G06Q10/10 , G06F2217/04 , Y10S707/99953 , Y10S707/99954
摘要： A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a "sub-netlist" within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.

3. 发明授权

US06815981B2 Programmable logic array integrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US06815981B2
公开(公告)日：2004-11-09
申请号：US10361477
申请日：2003-02-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

4. 发明授权

US5670895A Routing connections for programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路的路由连接
公开(公告)号：US5670895A
公开(公告)日：1997-09-23
申请号：US545084
申请日：1995-10-19
申请人： Peter J. Kazarian , Bruce B. Pedersen , Francis B. Heile , David Wolk Mendel
发明人： Peter J. Kazarian , Bruce B. Pedersen , Francis B. Heile , David Wolk Mendel
IPC分类号： H03K19/177 , H03K7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17704
摘要： Logic signal routability in programmable logic array integrated circuit devices is improved by selecting the possible interconnections between various resources on the device so that various constraints or goals are satisfied. Improving routability in this way tends to reduce instances in which desired interconnections are blocked by other connections that have already been made.
摘要翻译：可编程逻辑阵列集成电路器件中的逻辑信号可路由性通过选择器件上各种资源之间的可能的互连来改善，以便满足各种约束或目标。以这种方式改进可路由性倾向于减少所期望的互连被已经被其他连接阻挡的情况。

5. 发明授权

US06392438B1 Programmable logic array integrated circuit devices 有权
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US06392438B1
公开(公告)日：2002-05-21
申请号：US09684148
申请日：2000-10-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K1977
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

6. 发明授权

US6080204A Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing 失效
标题翻译：同时编译电子电路设计的方法和装置，通过使用并行处理同时二分割电子电路设计
公开(公告)号：US6080204A
公开(公告)日：2000-06-27
申请号：US958670
申请日：1997-10-27
申请人： David Wolk Mendel
发明人： David Wolk Mendel
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Disclosed are various techniques for deploying multiple processing resources, operating in parallel, to compile electronic designs. The disclosed methods identify "compilation tasks" that can be performed in isolation from the remainder of a large "compilation project." When one of these stand alone compilation tasks is identified, it can be temporarily segregated and performed by one or more processors which are not working on other tasks. Simultaneously, the remainder of the project compiles under one or more other processors. One class of severable compilation projects includes those projects that contain multiple full compilation tasks, each of which involves compiling a single design from start to finish. Another class of divisible compilation projects includes those projects in which the logical hierarchy of an electronic design provides the boundaries between isolated compilation tasks. Yet another class of divisible compilation projects are projects in which the tasks are divided out based upon an architecture of a target hardware device.
摘要翻译：公开了用于部署多个处理资源的各种技术，并行操作以编译电子设计。所公开的方法标识可以与大型“编译项目”的其余部分隔离执行的“编译任务”。当这些独立的编译任务之一被识别时，它可以被一个或多个不在其他任务上的处理器暂时隔离和执行。同时，该项目的其余部分在一个或多个其他处理器下编译。一类可分割的编译项目包括那些包含多个完整编译任务的项目，每个任务包括从头到尾编译单个设计。另一类可分割编译项目包括那些在电子设计的逻辑层次结构提供隔离编译任务之间的界限的项目。另一类可分割编译项目是根据目标硬件设备的架构划分任务的项目。

7. 发明授权

US6102964A Fitting for incremental compilation of electronic designs 失效
标题翻译：适用于电子设计的增量编译
公开(公告)号：US6102964A
公开(公告)日：2000-08-15
申请号：US958436
申请日：1997-10-27
申请人： John Tse , Fung Fung Lee , David Wolk Mendel
发明人： John Tse , Fung Fung Lee , David Wolk Mendel
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185 , G06F9/44 , G06F9/445 , G06F11/14 , G06F11/273 , G06F11/28 , G06F12/00 , G06F17/50 , G06Q10/06 , G06Q10/10 , H01L21/82
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F8/65 , G06F8/71 , G06Q10/06 , G06Q10/10 , G06F2217/04 , Y10S707/99953 , Y10S707/99954
摘要： A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design." The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions.If this fails, the compiler allows logic cells from the unchanged portion of the changed electronic design to shift by a limited amount to other logic elements within the target hardware device. At first, this shifting is fairly constrained in order to preserve as much of the original compilation's placement as possible. However, if fitting can not be accomplished under these constraints, gradually the constraints are lifted, until a fit is achieved.
摘要翻译：公开了一种用于在增量重新编译期间从电子设计有效地放置逻辑单元的技术。这是通过在重新编译过程中尽可能多地固定逻辑单元来实现的。要了解如何运作，认识不到“原创电子设计”已经完全编译。现在，用户对原始电子设计进行了一个或多个更改以产生“改变的电子设计”。所公开的技术适合改变的电子设计，在增量重新编译期间，而不会在原始电子设计的编译期间太多的先前适合的逻辑。最初，编译器尝试将电子设计的改变的部分的逻辑单元适配到硬件设备的可用逻辑元件，同时将来自改变的电子设计的未改变部分的逻辑单元限制到其原始位置。如果失败，编译器允许来自改变的电子设计的未改变部分的逻辑单元向目标硬件设备内的其他逻辑元件移动有限的量。起初，这种转变是相当有限的，以便尽可能多地保留原始的编译位置。然而，如果在这些约束条件下不能完成拟合，则逐渐地解除约束，直到实现拟合。

8. 发明授权

US5691653A Product term based programmable logic array devices with reduced control memory requirements 失效
标题翻译：基于产品术语的可编程逻辑阵列器件，具有降低的控制存储器要求
公开(公告)号：US5691653A
公开(公告)日：1997-11-25
申请号：US586087
申请日：1996-01-16
申请人： David Wolk Mendel
发明人： David Wolk Mendel
IPC分类号： H03K19/177 , H03K19/94 , H03K7/38
CPC分类号： H03K19/17708
摘要： The number of programmable control elements required in a programmable AND array for use in a product term based programmable logic array device is reduced by generally feeding only the true or complement of each input logic signal into the AND array on an associated main word line conductor. Auxiliary word line conductors are provided for those input logic signals that are required in both true and complement form. The number of auxiliary word line conductors is less than the number of main word line conductors, which can reduce the required number of programmable control elements as compared to a conventional programmable AND array in which both the true and complement of all input logic signals are fed into the array.
摘要翻译：通过将每个输入逻辑信号的真实或补码通常仅馈入相关联的主字线导体上的AND阵列，可减少用于基于产品项的可编程逻辑阵列器件中的可编程AND阵列中所需的可编程控制元件的数量。辅助字线导体被提供用于真实和补充形式所需的那些输入逻辑信号。辅助字线导体的数量小于主字线导体的数量，与传统的可编程AND阵列相比，可减少所需数量的可编程控制元件，其中所有输入逻辑信号的真和补两者均被馈送进入阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式