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1. 发明授权

US06392438B1 Programmable logic array integrated circuit devices 有权
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US06392438B1
公开(公告)日：2002-05-21
申请号：US09684148
申请日：2000-10-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K1977
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

2. 发明授权

US06225823B1 Input/output circuitry for programmable logic devices 有权
标题翻译：可编程逻辑器件的输入/输出电路
公开(公告)号：US06225823B1
公开(公告)日：2001-05-01
申请号：US09535635
申请日：2000-03-24
申请人： Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , David Edward Jefferson
发明人： Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , David Edward Jefferson
IPC分类号： H03K19177
CPC分类号： H03K19/17744
摘要： A programmable logic device has a plurality of conductors extending around its periphery for use in providing at least some of the signals needed for control of input/output (“I/O”) pins which are also disposed around the periphery of the device. These control signals may include clock signals, output enable signals, clock enable signals, clear signals, or the like. The conductors that thus extend around the periphery are segmented into plural segments that can either be used independently of one another or programmably stitched together and therefore used together.
摘要翻译：可编程逻辑器件具有围绕其周边延伸的多个导体，用于提供控制输入/输出（“I / O”）引脚所需的至少一些信号，该引脚也设置在器件周围。这些控制信号可以包括时钟信号，输出使能信号，时钟使能信号，清除信号等。因此，围绕周边延伸的导体被分割成多个段，其可以彼此独立地使用或可编程地缝合在一起，因此一起使用。

3. 发明授权

US5699020A Phase latched differential charge pump circuit and method 失效
标题翻译：相锁相差动电荷泵电路及方法
公开(公告)号：US5699020A
公开(公告)日：1997-12-16
申请号：US668577
申请日：1996-06-20
申请人： David Edward Jefferson
发明人： David Edward Jefferson
IPC分类号： H03L7/087 , H03L7/089 , H03L7/095 , H03L7/107 , H03L7/12
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/095 , H03L7/087 , Y10S331/02
摘要： A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for changing the strength of the lock after lock has been achieved. Before lock is achieved, the strength of the charge pump circuitry that controls the charge in the low-pass filter in the loop may be relatively weak. After lock has been achieved, the strength of the charge pump circuit may be increased so that the circuit can maintain its locked condition in a noisy environment.
摘要翻译：诸如延迟锁定环或锁相环的回路电路包括用于在实现锁定之后改变锁的强度的电路。在实现锁定之前，控制环路中的低通滤波器中的电荷的电荷泵电路的强度可能相对较弱。在实现锁定之后，可以增加电荷泵电路的强度，使得电路可以在嘈杂的环境中保持其锁定状态。

4. 发明授权

US06815981B2 Programmable logic array integrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US06815981B2
公开(公告)日：2004-11-09
申请号：US10361477
申请日：2003-02-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

5. 发明授权

US6107825A Input/output circuitry for programmable logic devices 失效
标题翻译：可编程逻辑器件的输入/输出电路
公开(公告)号：US6107825A
公开(公告)日：2000-08-22
申请号：US87630
申请日：1998-05-29
申请人： Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , David Edward Jefferson
发明人： Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , David Edward Jefferson
IPC分类号： H03K19/177
CPC分类号： H03K19/17744
摘要： A programmable logic device has a plurality of conductors extending around its periphery for use in providing at least some of the signals needed for control of input/output ("I/O") pins which are also disposed around the periphery of the device. These control signals may include clock signals, output enable signals, clock enable signals, clear signals, or the like. The conductors that thus extend around the periphery are segmented into plural segments that can either be used independently of one another or programmably stitched together and therefore used together.
摘要翻译：可编程逻辑器件具有围绕其周边延伸的多个导体，用于提供控制输入/输出（“I / O”）引脚所需的至少一些信号，该引脚也设置在器件周围。这些控制信号可以包括时钟信号，输出使能信号，时钟使能信号，清除信号等。因此，围绕周边延伸的导体被分割成多个段，其可以彼此独立地使用或可编程地缝合在一起，因此一起使用。

6. 发明授权

US5847617A Variable-path-length voltage-controlled oscillator circuit 失效
标题翻译：可变路径长度压控振荡器电路
公开(公告)号：US5847617A
公开(公告)日：1998-12-08
申请号：US909337
申请日：1997-08-11
申请人： Srinivas T. Reddy , David Edward Jefferson , Richard G. Cliff , Cameron McClintock
发明人： Srinivas T. Reddy , David Edward Jefferson , Richard G. Cliff , Cameron McClintock
IPC分类号： H03K3/03 , H03L7/099 , H03B5/24
CPC分类号： H03L7/0997 , H03K3/0315
摘要： A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.
摘要翻译：提供了可变路径长度的压控振荡器电路。振荡器电路具有由一系列压控逆变器级形成的环形振荡器。基于存储在存储器中的路径长度配置数据来选择环路的路径长度（即，逆变器级数）。所选择的路径长度决定了环形振荡器的额定或中心频率。通过改变环形振荡器路径中每个反相器级的延迟，振荡器电路的输出频率就关于该中心频率进行电压调谐。可以使用各种类型的压控变频器级，包括电流欠压级，可变容性负载逆变级和差分延迟逆变级。压控振荡器电路可用于可编程逻辑器件上的锁相环，用于频率合成或消除时钟偏移。

7. 发明授权

US5642082A Loop filter level detection circuit and method 失效
标题翻译：环路滤波器电平检测电路及方法
公开(公告)号：US5642082A
公开(公告)日：1997-06-24
申请号：US668265
申请日：1996-06-20
申请人： David Edward Jefferson
发明人： David Edward Jefferson
IPC分类号： H03L7/081 , H03L7/089 , H03L7/00
CPC分类号： H03L7/0891 , H03L7/081 , H03L7/0812
摘要： A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for detecting when the output signal of the low-pass filter in the loop has either risen to a voltage which is relatively close to the power voltage of the circuit or has fallen to a voltage which is relatively close to the ground voltage of the circuit. In either case the circuitry reverses the significance of the phase frequency detector output signals that control whether the output voltage of the low-pass filter rises or falls. Alternatively or in addition, the phase frequency detector may be reset. Coarser adjustments may be made to the loop circuit downstream from the low-pass filter in response to a recurrence of the low-pass filter output voltage reaching either of the detected voltages mentioned above.
摘要翻译：诸如延迟锁定环路或锁相环路的环路电路包括用于检测环路中的低通滤波器的输出信号何时已经升高到相对接近电路的电源电压的电压或具有下降到相对接近电路接地电压的电压。在任一种情况下，电路反转相位频率检测器输出信号的重要性，其控制低通滤波器的输出电压是上升还是下降。或者或另外，可以复位相位频率检测器。响应于低通滤波器输出电压的复发达到上述检测到的电压之一，可以对低通滤波器下游的环路电路进行更粗略的调整。

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