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1. 发明申请

US20100218155A1 Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design 失效
标题翻译：物理综合分层设计中的自动关键区域分配
公开(公告)号：US20100218155A1
公开(公告)日：2010-08-26
申请号：US12394035
申请日：2009-02-26
申请人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Hoaxing Ren
发明人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Hoaxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other.Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
摘要翻译：公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法，计算机程序产品和数据处理系统。为了准备全局优化，在单元级别的整个单元，宏级单元被分配一个“放置力”，其用于限制宏级单元从其当前位置的移动。还定义每个宏元素的移动边界，以便将给定宏元素中的组件保持在彼此相对接近。然后，通过力导向布局算法，在设计的“扁平化”模型上执行单元设计的优化/放置，同时遵循移动边界。在这种“扁平化”优化之后，放置的“单位级”单元被建模为阻塞，并且宏元素被单独地优化，同时尊重阻塞的位置。重复这个整个过程，直到单元布局的优化最终收敛。

2. 发明授权

US08656332B2 Automated critical area allocation in a physical synthesized hierarchical design 失效
标题翻译：物理合成分层设计中的自动关键区域分配
公开(公告)号：US08656332B2
公开(公告)日：2014-02-18
申请号：US12394035
申请日：2009-02-26
申请人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Haoxing Ren
发明人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Haoxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
摘要翻译：公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法，计算机程序产品和数据处理系统。为了准备全局优化，在单元级别的整个单元，宏级单元被分配一个“放置力”，其用于限制宏级单元从其当前位置的移动。还定义每个宏元素的移动边界，以便将给定宏元素中的组件保持在彼此相对接近。然后，通过力导向布局算法，在设计的“扁平化”模型上执行单元设计的优化/放置，同时遵循移动边界。在这种“扁平化”优化之后，放置的“单位级”单元被建模为阻塞，并且宏元素被单独地优化，同时尊重阻塞的位置。重复这个整个过程，直到单元布局的优化最终收敛。

3. 发明申请

US20090177870A1 Method and System for a Wiring-Efficient Permute Unit 失效
标题翻译：一种有效的宽带单元的方法和系统
公开(公告)号：US20090177870A1
公开(公告)日：2009-07-09
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F9/305 , G06F13/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

4. 发明授权

US08069195B2 Method and system for a wiring-efficient permute unit 失效
标题翻译：布线效率置换单元的方法和系统
公开(公告)号：US08069195B2
公开(公告)日：2011-11-29
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F7/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

5. 发明授权

US09632778B2 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry 有权
公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

6. 发明授权

US09575756B2 Predication in a vector processor 有权
标题翻译：矢量处理器中的预测
公开(公告)号：US09575756B2
公开(公告)日：2017-02-21
申请号：US13569349
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/30 , G06F9/38 , G06F15/80 , G11C7/10 , G11C8/12
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理器预测。一个方面包括用于有源存储器设备中的向量处理器预测的系统。该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。一个或多个掩码位从处理元件中的向量掩码寄存器访问。一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

7. 发明授权

US09569211B2 Predication in a vector processor 有权
标题翻译：矢量处理器中的预测
公开(公告)号：US09569211B2
公开(公告)日：2017-02-14
申请号：US13566129
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/30 , G06F9/38 , G06F15/80 , G11C7/10 , G11C8/12
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理器预测。一个方面包括一种用于包括存储器和处理元件的有源存储器件中的向量处理器预测的方法。该方法包括在处理元件中解码包括并行执行的多个子指令的指令。一个或多个掩码位从处理元件中的向量掩码寄存器访问。一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

8. 发明申请

US20140040601A1 PREDICATION IN A VECTOR PROCESSOR 有权
标题翻译：矢量处理器中的预测
公开(公告)号：US20140040601A1
公开(公告)日：2014-02-06
申请号：US13566129
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理器预测。一个方面包括一种用于包括存储器和处理元件的有源存储器件中的向量处理器预测的方法。该方法包括在处理元件中解码包括并行执行的多个子指令的指令。一个或多个掩码位从处理元件中的向量掩码寄存器访问。一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

9. 发明申请

US20100095087A1 Dynamic Data Driven Alignment and Data Formatting in a Floating-Point SIMD Architecture 有权
标题翻译：浮点数SIMD架构中动态数据驱动对齐和数据格式化
公开(公告)号：US20100095087A1
公开(公告)日：2010-04-15
申请号：US12250584
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F9/06
CPC分类号： G06F9/30036 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/3887
摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.
摘要翻译：为浮点SIMD架构提供动态数据驱动对齐和数据格式化的机制。至少两个操作数输入被输入到处理器的置换单元。每个操作数输入包含至少一个浮点值，在该浮点值上由置换单元执行置换操作。具有一起构成控制向量输入的多个浮点值的控制矢量输入被输入到处理器的置换单元，用于控制置换单元的置换操作。置换单元根据由构成控制向量输入的多个浮点值指定的置换模式对至少两个操作数输入执行置换操作。此外，置换操作的结果输出从处理单元输出到处理器的结果向量寄存器。

10. 发明申请

US20100095086A1 Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors 失效
标题翻译：基于与精简向量精简对应的地址动态对齐增强精度向量
公开(公告)号：US20100095086A1
公开(公告)日：2010-04-15
申请号：US12250599
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/3887
摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
摘要翻译：提供了基于减少的精度数据值对准增强精度向量的机制。接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。向量寄存器将数据存储为具有多个向量元素的向量。第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

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