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1. 发明授权

US08743973B2 Receiver resistor network for common-mode signaling 失效
标题翻译：用于共模信号的接收电阻网络
公开(公告)号：US08743973B2
公开(公告)日：2014-06-03
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入以及输出，以提供从在输入节点处接收的信号的共模分量得到的信号。

2. 发明申请

US20110293041A1 Receiver Resistor Network for Common-Mode Signaling 失效
标题翻译：用于共模信号的接收器电阻网络
公开(公告)号：US20110293041A1
公开(公告)日：2011-12-01
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04L27/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入端和输出端，以提供从在输入节点接收的信号的共模分量得到的信号。

3. 发明授权

US08836394B2 Method and apparatus for source-synchronous signaling 有权
标题翻译：源同步信令的方法和装置
公开(公告)号：US08836394B2
公开(公告)日：2014-09-16
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00 , H04L7/00 , H04L7/033 , G11C7/10
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

4. 发明申请

US20130249612A1 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING 有权
标题翻译：用于同源信号的方法和装置
公开(公告)号：US20130249612A1
公开(公告)日：2013-09-26
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

5. 发明申请

US20140043105A1 INTEGRATED CIRCUIT HAVING A MULTIPLYING INJECTION-LOCKED OSCILLATOR 审中-公开
标题翻译：具有多针注射锁止振荡器的集成电路
公开(公告)号：US20140043105A1
公开(公告)日：2014-02-13
申请号：US14000710
申请日：2012-04-18
申请人： Jared L. Zerbe , Barry W. Daly , Dustin T. Dunwell , Anthony C. Carusone , John C. Eble, III
发明人： Jared L. Zerbe , Barry W. Daly , Dustin T. Dunwell , Anthony C. Carusone , John C. Eble, III
IPC分类号： H03L7/24
CPC分类号： H03L7/24 , H03B27/00 , H03K3/0315 , H03K3/0322 , H03K5/133 , H03K5/1565
摘要： Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.
摘要翻译：描述了具有乘法注入锁定振荡器的方法和装置。一些实施例包括脉冲发生器和注射器以及一个或多个注入锁定的振荡器。脉冲发生器和注射器的输出可以注入到注入锁定振荡器的相应注入点。在包括多个注入锁定振荡器的实施例中，每个注入锁定振荡器的输出可以被注入到下一个注入锁定振荡器的相应注入点。一些实施例通过动态地修改注入锁定振荡器的环路长度和/或通过使用占空比校正器和/或通过复用/混合来自注入锁定振荡器的多个延迟元件的输出来减少确定性抖动。

6. 发明授权

US09154145B2 Integrated circuit having a multiplying injection-locked oscillator 有权
标题翻译：具有倍增注入锁定振荡器的集成电路
公开(公告)号：US09154145B2
公开(公告)日：2015-10-06
申请号：US14000710
申请日：2012-04-18
申请人： Jared L. Zerbe , Barry W. Daly , Dustin T. Dunwell , Anthony C. Carusone , John C. Eble, III
发明人： Jared L. Zerbe , Barry W. Daly , Dustin T. Dunwell , Anthony C. Carusone , John C. Eble, III
IPC分类号： H03L7/24 , H03K3/03
CPC分类号： H03L7/24 , H03B27/00 , H03K3/0315 , H03K3/0322 , H03K5/133 , H03K5/1565
摘要： Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.
摘要翻译：描述了具有乘法注入锁定振荡器的方法和装置。一些实施例包括脉冲发生器和注射器以及一个或多个注入锁定的振荡器。脉冲发生器和注射器的输出可以注入到注入锁定振荡器的相应注入点。在包括多个注入锁定振荡器的实施例中，每个注入锁定振荡器的输出可以被注入到下一个注入锁定振荡器的相应注入点。一些实施例通过动态地修改注入锁定振荡器的环路长度和/或通过使用占空比校正器和/或通过复用/混合来自注入锁定振荡器的多个延迟元件的输出来减少确定性抖动。

7. 发明申请

US20110051854A1 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION 有权
标题翻译：多线通信期间的错误检测和偏移消除
公开(公告)号：US20110051854A1
公开(公告)日：2011-03-03
申请号：US12920806
申请日：2009-02-19
申请人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
发明人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
IPC分类号： H04L27/06
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols, and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译：描述电路的实施例。在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，以及如果不平衡被检测到，它确定了错误条件。

8. 发明授权

US08462891B2 Error detection and offset cancellation during multi-wire communication 有权
标题翻译：多线通讯期间的错误检测和偏移消除
公开(公告)号：US08462891B2
公开(公告)日：2013-06-11
申请号：US12920806
申请日：2009-02-19
申请人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
发明人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
IPC分类号： H04L27/06
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译：描述电路的实施例。在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。此外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡以及M个符号集合中的第二值的实例的数量，并且如果不平衡是检测到，这会导致错误条件。

9. 发明授权

US09843309B2 Receiver with time-varying threshold voltage 有权
公开(公告)号：US09843309B2
公开(公告)日：2017-12-12
申请号：US13393314
申请日：2010-11-10
申请人： Jared L. Zerbe , Brian S. Leibowitz , Qi Lin
发明人： Jared L. Zerbe , Brian S. Leibowitz , Qi Lin
IPC分类号： H04L25/34 , H03K3/013 , G11C7/02 , H03K5/153 , H04L25/49 , H04L25/06 , H04L25/03
CPC分类号： H03K3/013 , G11C7/02 , H03K5/153 , H04L25/03057 , H04L25/066 , H04L25/4902 , H04L25/4917
摘要： A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

10. 发明授权

US08941420B2 Low-latency, frequency-agile clock multiplier 有权
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：US08941420B2
公开(公告)日：2015-01-27
申请号：US13983836
申请日：2012-05-24
申请人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
发明人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
IPC分类号： H03B19/00 , H03K5/00 , H03L7/06 , H03L7/099
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择时钟。

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