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1. 发明授权

US06310400B1 Apparatus for capacitively coupling electronic devices 失效
标题翻译：用于电容耦合电子设备的装置
公开(公告)号：US06310400B1
公开(公告)日：2001-10-30
申请号：US08999020
申请日：1997-12-29
申请人： Brian Doyle , Quat T. Vu , David B. Fraser
发明人： Brian Doyle , Quat T. Vu , David B. Fraser
IPC分类号： H01L2348
CPC分类号： H01L23/642 , H01L23/48 , H01L25/18 , H01L2224/16
摘要： A method and apparatus for capacitively coupling the input and output terminals of two semiconductor devices.
摘要翻译：一种用于电容耦合两个半导体器件的输入和输出端子的方法和装置。

2. 发明授权

US06790704B2 Method for capacitively coupling electronic devices 有权
标题翻译：电容耦合电子器件的方法
公开(公告)号：US06790704B2
公开(公告)日：2004-09-14
申请号：US09908016
申请日：2001-07-17
申请人： Brian Doyle , Quat T. Vu , David B. Fraser
发明人： Brian Doyle , Quat T. Vu , David B. Fraser
IPC分类号： H01L2144
CPC分类号： H01L23/642 , H01L23/48 , H01L25/18 , H01L2224/16
摘要： A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.
摘要翻译：描述了将第一半导体衬底上的第一组导电焊盘电耦合到第二半导体衬底上的第二组导电焊盘的方法。第一厚度的介电材料沉积在至少一组第一和第二组导电焊盘上。然后将第一和第二半导体衬底附接在一起，使得第一组和第二组衬垫基本上彼此平行对准，并且使得电介质材料设置在第一组和第二组导电衬垫之间。

3. 发明授权

US06303464B1 Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer 失效
标题翻译：用于通过电介质层中的封闭空隙减小互连系统电容的方法和结构
公开(公告)号：US06303464B1
公开(公告)日：2001-10-16
申请号：US08774382
申请日：1996-12-30
申请人： Eng T. Gaw , Quat T. Vu , David B. Fraser , Chien Chiang , Ian A. Young , Thomas N. D. Marieb
发明人： Eng T. Gaw , Quat T. Vu , David B. Fraser , Chien Chiang , Ian A. Young , Thomas N. D. Marieb
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.
摘要翻译：降低电容互连系统。第一金属层形成在形成在半导体衬底上的第一介电层上方的预定水平。第一金属层级形成多个互连线，其中每个互连线通过包括具有最高纵横比的沟槽的沟槽与每个相邻的互连线分开。在第一金属层和互连线之间的沟槽中形成第二电介质层，使得具有空隙尖端的封闭空隙与金属层的顶部基本一致地形成在至少每个沟槽中，其纵横比高于预定的最小纵横比，其中具有最高纵横比的沟槽中的封闭空隙具有至少占沟槽体积的15％的空隙体积。

4. 发明授权

US06689702B2 High dielectric constant metal oxide gate dielectrics 有权
标题翻译：高介电常数金属氧化物栅极电介质
公开(公告)号：US06689702B2
公开(公告)日：2004-02-10
申请号：US10304434
申请日：2002-11-25
申请人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
发明人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
IPC分类号： H01L21469
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28229 , H01L29/517
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.
摘要翻译：形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

5. 发明授权

US5886410A Interconnect structure with hard mask and low dielectric constant materials 失效
标题翻译：互连结构与硬掩模和低介电常数材料
公开(公告)号：US5886410A
公开(公告)日：1999-03-23
申请号：US670624
申请日：1996-06-26
申请人： Chien Chiang , Chuanbin Pan , Vicky M. Ochoa , Sychyi Fang , David B. Fraser , Joyce C. Sum , Gary William Ray , Jeremy A. Theil
发明人： Chien Chiang , Chuanbin Pan , Vicky M. Ochoa , Sychyi Fang , David B. Fraser , Joyce C. Sum , Gary William Ray , Jeremy A. Theil
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/485
CPC分类号： H01L23/5329 , H01L21/76802 , H01L21/7684 , H01L21/76877 , H01L23/5222 , H01L2924/0002
摘要： An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.
摘要翻译：提供互连系统。互连系统包括硅衬底和形成在硅衬底上的第一介电层。互连系统还包括形成在第一介电层上的至少两个导电线的第一级。所述互连系统还包括形成在所述至少两个导电线之间的低介电常数材料区域。互连系统还包括形成在聚合物区域上的第一硬掩模。

6. 发明授权

US5817572A Method for forming multileves interconnections for semiconductor fabrication 失效
标题翻译：用于形成用于半导体制造的多层互连的方法
公开(公告)号：US5817572A
公开(公告)日：1998-10-06
申请号：US768790
申请日：1996-12-18
申请人： Chien Chiang , David B. Fraser
发明人： Chien Chiang , David B. Fraser
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76843 , H01L21/76852 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L23/5329 , H01L21/76829 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53266 , H01L2924/0002 , Y10S438/945 , Y10S438/975
摘要： A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.
摘要翻译：描述了用于形成用于半导体制造和半导体器件的互连的方法具有这样的互连。第一图案化电介质层形成在半导体衬底之上并且具有填充有导电材料的第一开口。在第一电介质层上形成另一图案化电介质层，并且在至少一部分导电材料上具有第二开口。第一图案化电介质层可以在图案化其它图案化的介电层时用作蚀刻停止。此外，在形成另一个图案化的介电层之前，可以在第一图案化电介质层上方和导电材料之上形成电介质蚀刻停止层。该电介质蚀刻停止层可以在图案化其它图案化的介电层时用作蚀刻停止。第二开口露出电介质蚀刻停止层的一部分。去除电介质蚀刻停止层的暴露部分。第二个开口填充有导电材料。

7. 发明授权

US5612254A Methods of forming an interconnect on a semiconductor substrate 失效
标题翻译：在半导体衬底上形成互连的方法
公开(公告)号：US5612254A
公开(公告)日：1997-03-18
申请号：US905473
申请日：1992-06-29
申请人： Xiao-Chun Mu , Srinivasan Sivaram , Donald S. Gardner , David B. Fraser
发明人： Xiao-Chun Mu , Srinivasan Sivaram , Donald S. Gardner , David B. Fraser
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76807 , H01L21/76877 , H01L23/5226 , H01L23/5329 , H01L2221/1036 , H01L2924/0002
摘要： A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.
摘要翻译：描述了在半导体器件中的预制图形通道内形成互连的装置和方法。本发明包括在半导体器件内形成互连通道的方法。第一电介质层沉积在衬底上并被图案化以形成随后用接触插塞填充的接触开口。在图案化的第一介电层和接触插塞上沉积第二介电层。图案化第二电介质层以形成互连通道，其中第一介电层用作蚀刻停止件以防止蚀刻基板。本发明还包括形成互连的方法。将电介质层沉积在衬底上并图案化以形成互连教堂。金属层沉积在图案化的介电层上并且在互连通道内。金属层用碱性溶液抛光以除去不在互连教堂内的金属层以形成互连。本发明还包括在氮化硅层上形成互连的方法。氮化硅层沉积在半导体衬底上并被图案化以形成随后用导电材料填充的接触开口。金属层沉积在图案化的氮化硅层和接触插塞上，并被图案化以形成互连，使得所有互连都位于接触插塞和图案化的氮化硅层的一部分上。

8. 发明授权

US06998357B2 High dielectric constant metal oxide gate dielectrics 失效
公开(公告)号：US06998357B2
公开(公告)日：2006-02-14
申请号：US10646034
申请日：2003-08-22
申请人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
发明人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
IPC分类号： H01L21/469
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28229 , H01L29/517
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

9. 发明授权

US06709885B2 Method of fabricating image sensors using a thin film photodiode above active CMOS circuitry 有权
标题翻译：使用有源CMOS电路上的薄膜光电二极管制造图像传感器的方法
公开(公告)号：US06709885B2
公开(公告)日：2004-03-23
申请号：US10280253
申请日：2002-10-25
申请人： Jack S. Uppal , David B. Fraser , Stephen Bradford Gospe , Kevin M. Connolly
发明人： Jack S. Uppal , David B. Fraser , Stephen Bradford Gospe , Kevin M. Connolly
IPC分类号： H01L2100
CPC分类号： H01L27/14643 , H01L27/14665
摘要： A method of fabricating an image sensor having pin photodiodes residing vertically atop underlying CMOS control circuitry. In the preferred technique, pin photodiodes fabricated in amorphous silicon are utilized.
摘要翻译：一种制造具有垂直位于底层CMOS控制电路上的引脚光电二极管的图像传感器的方法。在优选的技术中，使用在非晶硅中制造的pin光电二极管。

10. 发明授权

US06501065B1 Image sensor using a thin film photodiode above active CMOS circuitry 有权
标题翻译：图像传感器使用有源CMOS电路上的薄膜光电二极管
公开(公告)号：US06501065B1
公开(公告)日：2002-12-31
申请号：US09474177
申请日：1999-12-29
申请人： Jack S. Uppal , David B. Fraser , Stephen Bradford Gospe , Kevin M. Connolly
发明人： Jack S. Uppal , David B. Fraser , Stephen Bradford Gospe , Kevin M. Connolly
IPC分类号： H01L3100
CPC分类号： H01L27/14643 , H01L27/14665
摘要： An image sensor having pin photodiodes residing vertically atop underlying CMOS control circuitry. In the preferred technique, pin photodiodes fabricated in amorphous silicon are utilized.
摘要翻译：具有垂直位于底层CMOS控制电路上的引脚光电二极管的图像传感器。在优选的技术中，使用在非晶硅中制造的pin光电二极管。

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