专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06689702B2 High dielectric constant metal oxide gate dielectrics 有权
标题翻译：高介电常数金属氧化物栅极电介质
公开(公告)号：US06689702B2
公开(公告)日：2004-02-10
申请号：US10304434
申请日：2002-11-25
申请人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
发明人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
IPC分类号： H01L21469
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28229 , H01L29/517
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.
摘要翻译：形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

2. 发明授权

US06998357B2 High dielectric constant metal oxide gate dielectrics 失效
公开(公告)号：US06998357B2
公开(公告)日：2006-02-14
申请号：US10646034
申请日：2003-08-22
申请人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
发明人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
IPC分类号： H01L21/469
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28229 , H01L29/517
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

3. 发明授权

US06528856B1 High dielectric constant metal oxide gate dielectrics 有权
标题翻译：高介电常数金属氧化物栅极电介质
公开(公告)号：US06528856B1
公开(公告)日：2003-03-04
申请号：US09212773
申请日：1998-12-15
申请人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
发明人： Gang Bai , David B. Fraser , Brian S. Doyle , Peng Cheng , Chunlin Liang
IPC分类号： H01L2976
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28229 , H01L29/517
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.
摘要翻译：形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

4. 发明授权

US6022815A Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique 失效
标题翻译：使用掩模边缘栅极定义技术制造下一个最小尺寸晶体管栅极的方法
公开(公告)号：US6022815A
公开(公告)日：2000-02-08
申请号：US775412
申请日：1996-12-31
申请人： Brian S. Doyle , Chunlin Liang , Peng Cheng , Qi-De Qian
发明人： Brian S. Doyle , Chunlin Liang , Peng Cheng , Qi-De Qian
IPC分类号： H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/8234 , H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/823456
摘要： A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric material is formed on the substrate. A layer of electrically conductive material is formed over the gate dielectric material. A first mask is used to form a hard mask. A layer of first spacer material is deposited over the existing structures, and the layer of first spacer material is etched back to form spacers adjacent to the hard mask. The width of the first spacers determines the minimum size gate length. A layer of second spacer material is deposited over the existing structures, including the hard mask and first spacers. The layer of second spacer material is etched back to form a second set of spacers adjacent to the first spacers. The width of the first and second spacers together determine the next-to-minimum size gate length. A second mask is used to protect the portion of the second spacers which are to be used to define next-to-minimum size gates, and the unprotected second spacers and the hard mask are removed. The exposed electrically conductive material is removed. The remaining spacers are then removed, leaving minimum size and next-to-minimum size gates.
摘要翻译：公开了使用无平滑工艺制造最小尺寸和接下来尺寸的导电构件的方法。提供衬底，并且在衬底上形成栅极电介质材料层。在栅极电介质材料上方形成一层导电材料。使用第一个掩模形成硬掩模。在现有结构上沉积第一间隔物层，并且将第一间隔物材料层回蚀刻以形成与硬掩模相邻的间隔物。第一间隔物的宽度决定了栅极长度的最小尺寸。在现有结构上沉积第二间隔物层，包括硬掩模和第一间隔物。第二间隔物材料层被回蚀刻以形成邻近第一间隔物的第二组间隔物。第一和第二间隔物的宽度一起确定下一个至最小尺寸的栅极长度。使用第二掩模来保护用于限定下一个至最小尺寸的门的第二间隔物的部分，并且去除未受保护的第二间隔物和硬掩模。暴露的导电材料被去除。然后移除剩余的间隔物，留下最小尺寸和下至最小尺寸的门。

5. 发明申请

US20050087820A1 High dielectric constant metal oxide gate dielectrics 失效
标题翻译：高介电常数金属氧化物栅极电介质
公开(公告)号：US20050087820A1
公开(公告)日：2005-04-28
申请号：US10646034
申请日：2003-08-22
申请人： Gang Bai , David Fraser , Brian Doyle , Peng Cheng , Chunlin Liang
发明人： Gang Bai , David Fraser , Brian Doyle , Peng Cheng , Chunlin Liang
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8238 , H01L29/76
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28229 , H01L29/517
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.
摘要翻译：形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

6. 发明授权

US06222254B1 Thermal conducting trench in a semiconductor structure and method for forming the same 失效
标题翻译：半导体结构中的导热沟槽及其形成方法
公开(公告)号：US06222254B1
公开(公告)日：2001-04-24
申请号：US08829860
申请日：1997-03-31
申请人： Chunlin Liang , Brian S. Doyle
发明人： Chunlin Liang , Brian S. Doyle
IPC分类号： H01L2972
CPC分类号： H01L29/1083 , H01L21/76224 , H01L21/763 , H01L23/3677 , H01L29/41766 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.
摘要翻译：本发明涉及在半导体衬底中形成填充有导热材料的沟槽的方法。在一个实施例中，该方法包括用导热材料填充沟槽的一部分并将接触图案化成导热材料。本发明还涉及半导体器件。在一个实施例中，半导体器件具有限定单元区域的沟槽，其中沟槽的一部分包括导热材料和与导热材料的接触。本发明还涉及半导体器件和形成具有作为导热材料的层间电介质的半导体器件的方法。

7. 发明授权

US07187044B2 Complementary metal gate electrode technology 有权
标题翻译：互补金属栅电极技术
公开(公告)号：US07187044B2
公开(公告)日：2007-03-06
申请号：US09517705
申请日：2000-03-02
申请人： Chunlin Liang , Gang Bai
发明人： Chunlin Liang , Gang Bai
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.
摘要翻译：一种制造电路器件的方法，包括：第一晶体管，其具有覆盖在半导体衬底的第一区域上的第一栅极电介质的第一金属栅电极。第一栅电极具有对应于P型硅和N型硅之一的功函数的功函数。电路装置还包括耦合到第一晶体管的第二晶体管。第二晶体管在半导体衬底的第二区域上的第二栅极电介质上具有第二金属栅电极。第二栅极金属栅电极具有对应于另一个P型硅和N型硅的功函数的功函数。

8. 发明授权

US06794232B2 Method of making MOSFET gate electrodes with tuned work function 有权
标题翻译：制造具有调谐功能的MOSFET栅电极的方法
公开(公告)号：US06794232B2
公开(公告)日：2004-09-21
申请号：US10383842
申请日：2003-03-07
申请人： Jun-Fei Zheng , Brian Doyle , Gang Bai , Chunlin Liang
发明人： Jun-Fei Zheng , Brian Doyle , Gang Bai , Chunlin Liang
IPC分类号： H01I21337
CPC分类号： H01L21/82345 , H01L21/823425 , H01L27/088
摘要： Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.
摘要翻译：具有至少两层材料的栅电极的绝缘栅场效应晶体管提供类似于掺杂多晶硅的栅电极功函数值，消除多余耗效应并且还基本上防止杂质扩散入栅电介质。公开了用于n沟道FET的相对厚的Al和薄TiN的双层堆叠以及相对厚的Pd和薄TiN的双层堆叠，或者用于p沟道FET的相对厚的Pd和薄TaN。改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。

9. 发明授权

US07223992B2 Thermal conducting trench in a semiconductor structure 有权
标题翻译：半导体结构中的导热沟槽
公开(公告)号：US07223992B2
公开(公告)日：2007-05-29
申请号：US11331321
申请日：2006-01-11
申请人： Chunlin Liang , Brian S. Doyle
发明人： Chunlin Liang , Brian S. Doyle
IPC分类号： H01L47/00 , H01L29/148
CPC分类号： H01L21/76801 , H01L21/76224 , H01L21/763 , H01L23/367 , H01L23/3677 , H01L29/1083 , H01L29/41766 , H01L29/78 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.
摘要翻译：本发明涉及在半导体衬底中填充有导热材料的沟槽。在一个实施例中，半导体器件具有限定单元区域的沟槽，其中沟槽的一部分包括导热材料和与导热材料的接触。本发明还涉及半导体器件和形成具有作为导热材料的层间电介质的半导体器件的方法。

10. 发明授权

US07067406B2 Thermal conducting trench in a semiconductor structure and method for forming the same 失效
标题翻译：半导体结构中的导热沟槽及其形成方法
公开(公告)号：US07067406B2
公开(公告)日：2006-06-27
申请号：US10632578
申请日：2003-07-31
申请人： Chunlin Liang , Brian S. Doyle
发明人： Chunlin Liang , Brian S. Doyle
IPC分类号： H01L21/20
CPC分类号： H01L21/76801 , H01L21/76224 , H01L21/763 , H01L23/367 , H01L23/3677 , H01L29/1083 , H01L29/41766 , H01L29/78 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.
摘要翻译：本发明涉及在半导体衬底中形成填充有导热材料的沟槽的方法。在一个实施例中，该方法包括用导热材料填充沟槽的一部分并将接触图案化成导热材料。本发明还涉及半导体器件。在一个实施例中，半导体器件具有限定单元区域的沟槽，其中沟槽的一部分包括导热材料和与导热材料的接触。本发明还涉及半导体器件和形成具有作为导热材料的层间电介质的半导体器件的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式