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1. 发明授权

US06781064B1 Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same 失效
标题翻译：具有无玻璃非导电层的电子器件封装的印刷电路板及其形成方法
公开(公告)号：US06781064B1
公开(公告)日：2004-08-24
申请号：US09342584
申请日：1999-06-29
申请人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
发明人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
IPC分类号： H05K103
CPC分类号： H01L23/564 , H01L21/481 , H01L23/498 , H01L23/49894 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/036 , H05K1/0366 , H05K3/429 , H05K3/4626 , H05K3/4641 , H05K2201/0195 , H05K2201/0769 , H05K2201/09718 , H05K2201/09881 , H01L2924/00014 , H01L2924/00012
摘要： A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.
摘要翻译：一种用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板。该印刷电路板包括一个无玻璃的电介质，用于分离和绝缘电源芯，电路或电镀通孔，以防止导电材料沿玻璃基预浸料衬底迁移引起的短路。

2. 发明授权

US06664485B2 Full additive process with filled plated through holes 有权
标题翻译：完全添加过程，填充电镀通孔
公开(公告)号：US06664485B2
公开(公告)日：2003-12-16
申请号：US09778702
申请日：2001-02-07
申请人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
发明人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
IPC分类号： H05K111
CPC分类号： H05K3/0094 , B32B7/04 , H05K1/0306 , H05K1/113 , H05K3/0023 , H05K3/045 , H05K3/184 , H05K3/4053 , H05K3/4069 , H05K3/426 , H05K3/427 , H05K3/4605 , H05K2201/0154 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10734 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0353 , H05K2203/1152 , Y10T29/49126 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： The present invention provides a printed circuit board and a method for the production of a printed circuit board having fine-line circuitry and greater aspect ratio on a subcomposite with plated through holes. A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.
摘要翻译：本发明提供了一种印刷电路板和一种在具有电镀通孔的子复合体上制造具有细线电路和更大纵横比的印刷电路板的方法。一种方法提供在具有填充的电镀通孔的子复合材料上的添加电镀。在电穿孔和填充通孔之后，通过无电沉积实现细线电路。精细线路电路可以通过无地电镀通孔，从而增加纵横比和用于附加部件和布线的可用表面积。

3. 发明授权

US06418616B2 Full additive process with filled plated through holes 失效
标题翻译：完全添加过程，填充电镀通孔
公开(公告)号：US06418616B2
公开(公告)日：2002-07-16
申请号：US09795852
申请日：2001-02-28
申请人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
发明人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
IPC分类号： H01K310
CPC分类号： H05K3/0094 , B32B7/04 , H05K1/0306 , H05K1/113 , H05K3/0023 , H05K3/045 , H05K3/184 , H05K3/4053 , H05K3/4069 , H05K3/426 , H05K3/427 , H05K3/4605 , H05K2201/0154 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10734 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0353 , H05K2203/1152 , Y10T29/49126 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.
摘要翻译：一种方法提供在具有填充的电镀通孔的子复合材料上的添加电镀。在电穿孔和填充通孔之后，通过无电沉积实现细线电路。精细线路电路可以通过无地电镀通孔，从而增加纵横比和用于附加部件和布线的可用表面积。

4. 发明授权

US06195883B1 Full additive process with filled plated through holes 失效
标题翻译：完全添加过程，填充电镀通孔
公开(公告)号：US06195883B1
公开(公告)日：2001-03-06
申请号：US09047984
申请日：1998-03-25
申请人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
发明人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
IPC分类号： H01K310
CPC分类号： H05K3/0094 , B32B7/04 , H05K1/0306 , H05K1/113 , H05K3/0023 , H05K3/045 , H05K3/184 , H05K3/4053 , H05K3/4069 , H05K3/426 , H05K3/427 , H05K3/4605 , H05K2201/0154 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10734 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0353 , H05K2203/1152 , Y10T29/49126 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.
摘要翻译：一种方法提供在具有填充的电镀通孔的子复合材料上的添加电镀。在电穿孔和填充通孔之后，通过无电沉积实现细线电路。精细线路电路可以通过无地电镀通孔，从而增加纵横比和用于附加部件和布线的可用表面积。

5. 发明授权

US07353590B2 Method of forming printed circuit card 失效
标题翻译：形成印刷电路卡的方法
公开(公告)号：US07353590B2
公开(公告)日：2008-04-08
申请号：US11224191
申请日：2005-09-12
申请人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
发明人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
IPC分类号： H05K3/36
CPC分类号： H05K3/445 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L2924/0002 , H05K1/056 , H05K1/113 , H05K3/0023 , H05K3/0052 , H05K3/0094 , H05K3/06 , H05K3/108 , H05K3/426 , H05K3/429 , H05K3/44 , H05K3/4623 , H05K3/4641 , H05K2201/0919 , H05K2201/09536 , H05K2201/09554 , H05K2201/096 , H05K2201/10734 , H05K2203/0323 , H05K2203/0574 , H05K2203/0733 , H05K2203/1394 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
摘要翻译：提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路卡的方法。光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。边框可以在卡的周围，包括从电介质层之一的边缘终止的金属层。提供带有间隙孔的铜箔。第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。开发了通孔，在两个电介质层中对其进行图案化。可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

6. 发明授权

US06521844B1 Through hole in a photoimageable dielectric structure with wired and uncured dielectric 失效
标题翻译：透光电介质结构中的通孔，有线和未固化电介质
公开(公告)号：US06521844B1
公开(公告)日：2003-02-18
申请号：US09430076
申请日：1999-10-29
申请人： Stephen J. Fuerniss , Gary Johansson , Ross W. Keesler , John M. Lauffer , Voya R. Markovich , Peter A. Moschak , David J. Russell , William E. Wilson
发明人： Stephen J. Fuerniss , Gary Johansson , Ross W. Keesler , John M. Lauffer , Voya R. Markovich , Peter A. Moschak , David J. Russell , William E. Wilson
IPC分类号： H05K100
CPC分类号： H05K3/0023 , H05K1/056 , H05K3/445 , H05K3/4641 , H05K2203/1476 , Y10T29/49165
摘要： An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remaining volume of the PID material circumscribing the annular volume. The cylindrical volume may include a via. The structure can include a power plane.
摘要翻译：电子结构。电子结构包括一层。该层包括：圆柱体积; 完全固化的圆环体积的环绕光学成像的电介质（PID）材料; 以及围绕环形体积的PID材料的部分固化的剩余容积。圆柱体积可以包括通孔。该结构可以包括电力平面。

7. 发明授权

US06479093B2 Composite laminate circuit structure and methods of interconnecting the same 失效
标题翻译：复合层压电路结构及其相互连接方法
公开(公告)号：US06479093B2
公开(公告)日：2002-11-12
申请号：US10062100
申请日：2002-01-31
申请人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
IPC分类号： B05D512
CPC分类号： H05K3/462 , H01R4/26 , H05K3/0023 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0307 , Y10S428/901 , Y10T156/1089 , Y10T428/24917
摘要： A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.
摘要翻译：提供了一种层叠电路结构组件，其包括至少两个模块化电路化的平面子组件; 位于每个子组件之间的接合层，并且其中所述子组件和接合层与来自可结合的可固化电介质的固化电介质结合在一起。子组件和接合层与可结合的导电材料电互连。接合层包括围绕内部导电层设置的电介质层。导电层具有通孔，并且介电层各自具有比导电层中的通孔更小的直径的通孔，并且与导电层中的通孔对准。通孔填充有电可焊接的导电材料，用于在子组件之间提供电接触。

8. 发明授权

US06204453B1 Two signal one power plane circuit board 有权
标题翻译：两个信号一个电源平面电路板
公开(公告)号：US06204453B1
公开(公告)日：2001-03-20
申请号：US09203956
申请日：1998-12-02
申请人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
发明人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
IPC分类号： H05K103
CPC分类号： H05K3/44 , H05K1/056 , H05K3/0023 , H05K3/108 , H05K3/426 , H05K3/445 , H05K2201/09554 , H05K2203/0733
摘要： A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.
摘要翻译：形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。铜箔上设有间隙孔。可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

9. 发明授权

US06986198B2 Method of forming printed circuit card 失效
标题翻译：形成印刷电路卡的方法
公开(公告)号：US06986198B2
公开(公告)日：2006-01-17
申请号：US10744142
申请日：2003-12-22
申请人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
发明人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
IPC分类号： H05K3/36
CPC分类号： H05K3/445 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L2924/0002 , H05K1/056 , H05K1/113 , H05K3/0023 , H05K3/0052 , H05K3/0094 , H05K3/06 , H05K3/108 , H05K3/426 , H05K3/429 , H05K3/44 , H05K3/4623 , H05K3/4641 , H05K2201/0919 , H05K2201/09536 , H05K2201/09554 , H05K2201/096 , H05K2201/10734 , H05K2203/0323 , H05K2203/0574 , H05K2203/0733 , H05K2203/1394 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer termination in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
摘要翻译：提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路卡的方法。通过孔穿过的光刻金属填充通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。边框可以在卡周围，包括从电介质层之一的边缘终止的金属层。提供带有间隙孔的铜箔。第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。开发了通孔，在两个电介质层中对其进行图案化。可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

10. 发明授权

US07381587B2 Method of making circuitized substrate 有权
标题翻译：制造电路化基板的方法
公开(公告)号：US07381587B2
公开(公告)日：2008-06-03
申请号：US11324432
申请日：2006-01-04
申请人： Robert M. Japp , John M. Lauffer , Voya R. Markovich , William E. Wilson
发明人： Robert M. Japp , John M. Lauffer , Voya R. Markovich , William E. Wilson
IPC分类号： H01L21/00
CPC分类号： H05K3/4641 , H05K3/429 , H05K2203/068
摘要： A method of making a circuitized substrate and an electrical assembly utilizing same in which the substrate is comprised of at least two sub-composites in which the dielectric material of at least one of these sub-composites is heated during bonding (e.g., lamination) to the other sufficiently to cause the dielectric material to flow into and substantially fill openings in a conductive layer for the bonded structure. Conductive thru-holes are formed within the bonded structure to couple selected ones of the structure's conductive layers. Formation of an electrical assembly is possible by positioning one or more electrical components (e.g., semiconductor chips or chip carriers) on the final structure and electrically coupling these to the structure's external circuitry.
摘要翻译：一种制造电路化基板的方法和使用其的电气组件，其中基板由至少两个亚复合材料构成，其中这些亚复合材料中的至少一个的介电材料在粘合（例如，层压）期间被加热到另一个足以使电介质材料流入并基本上填充用于接合结构的导电层中的开口。导电通孔形成在接合结构内，以耦合所选择的结构导电层。通过将一个或多个电气部件（例如，半导体芯片或芯片载体）定位在最终结构上并将其电耦合到结构的外部电路，可以形成电组件。

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