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1. 发明授权

US08405229B2 Electronic package including high density interposer and circuitized substrate assembly utilizing same 有权
标题翻译：电子封装包括高密度插入器和利用其的电路化基板组件
公开(公告)号：US08405229B2
公开(公告)日：2013-03-26
申请号：US12592682
申请日：2009-11-30
申请人： Timothy Antesberger , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H01L29/40
CPC分类号： H01L23/49833 , H01L23/49822 , H01L23/49827 , H01L24/19 , H01L24/20 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided.
摘要翻译：一种用于将包装的电子设备（例如，半导体芯片）的导体的高密度图案互连到电路化基板（例如，PCB）上的较不致密的导体图案的电子封装，该封装在一个实施例中包括单个薄的电介质层（例如，Kapton），其中具有高密度图案的开口和相对表面上的电路图案，其包括导体的高密度图案和不太密集的导体图案。导电构件位于开口中，以将电子装置的导体与包装件定位在其上的电路化衬底的导体电互连。在另一个实施例中，插入器包括结合到第一介质层的第二电介质层，其中导电构件延伸穿过第二层以连接到较小密集的电路化衬底导体图案。还提供了使用本发明的电子封装件的电路化基板组件。

2. 发明授权

US08245392B2 Method of making high density interposer and electronic package utilizing same 有权
标题翻译：制造高密度插入件的方法和使用其的电子封装
公开(公告)号：US08245392B2
公开(公告)日：2012-08-21
申请号：US12592734
申请日：2009-12-01
申请人： Timothy Antesberger , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H05K3/4623 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L24/19 , H01L24/20 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H05K3/0035 , H05K3/305 , H05K2201/0154 , H05K2201/10378 , H05K2201/10674 , H05K2203/061 , H05K2203/1469 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , H01L2924/00012 , H01L2924/00
摘要： A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.
摘要翻译：一种制造电子封装的方法，其设计用于互连电子器件（例如，半导体芯片）的导体的高密度图案和托管电路化基板（例如，芯片载体，PCB）的导体的较不致密的图案。在一个实施例中，该方法包括将芯片接合到单个电介质层，在该层的一个表面上形成高密度图案的导体，在该层中形成开口，然后沉积冶金以形成期望的电路图案，接合并且电耦合到另一托管基板上的对应图案。根据本发明的另一个实施例，提供了一种使用双层插入器的电子封装。还提供了使用根据本发明的教导制造的电子封装制造电路化基板组件的方法。

3. 发明申请

US20110127664A1 Electronic package including high density interposer and circuitized substrate assembly utilizing same 有权
标题翻译：电子封装包括高密度插入器和利用其的电路化基板组件
公开(公告)号：US20110127664A1
公开(公告)日：2011-06-02
申请号：US12592682
申请日：2009-11-30
申请人： Timothy Antesberger , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H01L23/48 , H01L23/498
CPC分类号： H01L23/49833 , H01L23/49822 , H01L23/49827 , H01L24/19 , H01L24/20 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01067 , H01L2924/01075 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An electronic package for interconnecting a high density pattern of conductors of an electronic device (e.g., semiconductor chip) of the package and a less dense pattern of conductors on a circuitized substrate (e.g., PCB), the package including in one embodiment but a single thin dielectric layer (e.g., Kapton) with a high density pattern of openings therein and a circuit pattern on an opposing surface which includes both a high density pattern of conductors and a less dense pattern of conductors. Conductive members are positioned in the openings to electrically interconnect conductors of the electronic device to conductors of the circuitized substrate when the package is positioned thereon. In another embodiment, the interposer includes a second dielectric layer bonded to the first, with conductive members extending through the second layer to connect to the less dense pattern of circuitized substrate conductors. Circuitized substrate assemblies using the electronic packages of the invention are also provided.
摘要翻译：一种用于将包装的电子设备（例如，半导体芯片）的导体的高密度图案互连到电路化基板（例如，PCB）上的较不致密的导体图案的电子封装，该封装在一个实施例中包括单个薄的电介质层（例如，Kapton），其中具有高密度图案的开口和相对表面上的电路图案，其包括导体的高密度图案和不太密集的导体图案。导电构件位于开口中，以将电子装置的导体与包装件定位在其上的电路化衬底的导体电互连。在另一个实施例中，插入器包括结合到第一介质层的第二电介质层，其中导电构件延伸穿过第二层以连接到较小密集的电路化衬底导体图案。还提供了使用本发明的电子封装件的电路化基板组件。

4. 发明授权

US07328502B2 Apparatus for making circuitized substrates in a continuous manner 失效
标题翻译：用于以连续方式制造电路化基板的装置
公开(公告)号：US07328502B2
公开(公告)日：2008-02-12
申请号：US11882625
申请日：2007-08-03
申请人： John M. Lauffer , Voya R. Markovich , James W. Orband , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , James W. Orband , William E. Wilson
IPC分类号： B23P19/00
CPC分类号： H05K3/44 , H05K3/064 , H05K3/4069 , H05K3/427 , H05K3/445 , H05K3/462 , H05K3/4641 , H05K2201/0355 , H05K2201/09536 , H05K2201/096 , H05K2201/10378 , H05K2203/0143 , H05K2203/068 , H05K2203/1545 , H05K2203/1572 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T29/53161 , Y10T29/5317 , Y10T29/53204
摘要： Apparatus for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can then be individually bonded to other, like substrates to form a larger multi-layered substrate with a plurality of conductive thru-holes, conductive and dielectric layers as part thereof.
摘要翻译：用于使用连续辊格式制造电路化衬底的装置，其中导体和电介质层被馈送到设备中，结合并传递到其他附近的工作站，其中发生诸如孔形成，电路化和最终分段的各种过程。所得到的衬底然后可以单独地结合到其它类似衬底，以形成具有多个导电通孔，较大导电孔和介电层作为其一部分的较大的多层衬底。

5. 发明授权

US07293355B2 Apparatus and method for making circuitized substrates in a continuous manner 有权
标题翻译：以连续方式制造电路化基板的装置和方法
公开(公告)号：US07293355B2
公开(公告)日：2007-11-13
申请号：US11110919
申请日：2005-04-21
申请人： John M. Lauffer , Voya R. Markovich , James W. Orband , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , James W. Orband , William E. Wilson
IPC分类号： H01K3/10
CPC分类号： H05K3/44 , H05K3/064 , H05K3/4069 , H05K3/427 , H05K3/445 , H05K3/462 , H05K3/4641 , H05K2201/0355 , H05K2201/09536 , H05K2201/096 , H05K2201/10378 , H05K2203/0143 , H05K2203/068 , H05K2203/1545 , H05K2203/1572 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T29/53161 , Y10T29/5317 , Y10T29/53204
摘要： Apparatus and method for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can then be individually bonded to other, like substrates to form a larger multi-layered substrate with a plurality of conductive thru-holes, conductive and dielectric layers as part thereof.
摘要翻译：使用连续辊格式制造电路化基片的装置和方法，其中导体和电介质层被馈送到装置中，结合并传递到其他附近的工作站，其中各种工艺如孔形成，电路化和最终分割发生。所得到的衬底然后可以单独地结合到其它类似衬底，以形成具有多个导电通孔，较大导电孔和介电层作为其一部分的较大多层衬底。

6. 发明授权

US06852152B2 Colloidal seed formulation for printed circuit board metallization 失效
标题翻译：用于印刷电路板金属化的胶体种子配方
公开(公告)号：US06852152B2
公开(公告)日：2005-02-08
申请号：US10253679
申请日：2002-09-24
申请人： Raymond T. Galasco , Roy H. Magnuson , Voya R. Markovich , Thomas R. Miller , Anita Sargent , William E. Wilson
发明人： Raymond T. Galasco , Roy H. Magnuson , Voya R. Markovich , Thomas R. Miller , Anita Sargent , William E. Wilson
IPC分类号： C23C18/28 , H05K3/18 , C23C18/30
CPC分类号： C23C18/28 , H05K3/181
摘要： A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C30H50O10, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.
摘要翻译：提供了一种用于在非电镀过程中催化活化非导电电介质基片的表面的胶态金属种子制剂。胶态金属种子制剂包括氯化亚锡，氯化钯，HCl和选自二苯氧基二磺酸或其碱金属或碱土金属盐，C30H50O10，醇烷氧基化物及其混合物的表面活性剂。还提供了使用胶体金属种子制剂将导电金属化学镀在非导电电介质基底上的方法。

7. 发明授权

US06451509B2 Composite laminate circuit structure and method of forming the same 有权
标题翻译：复合层压电路结构及其形成方法
公开(公告)号：US06451509B2
公开(公告)日：2002-09-17
申请号：US09753015
申请日：2001-01-02
申请人： Ross W. Keesler , Voya R. Markovich , Jim P. Paoletti , Marybeth Perrino , William E. Wilson
发明人： Ross W. Keesler , Voya R. Markovich , Jim P. Paoletti , Marybeth Perrino , William E. Wilson
IPC分类号： H05K111
CPC分类号： H05K3/4641 , H05K3/0023 , H05K3/429 , H05K3/4623 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09809
摘要： A method forming a composite laminate structure includes providing first and second circuit board element each having circuitry on at least one face thereof and plated through holes. A voltage plane element is provided having at least one voltage plane having opposite faces with layers of partially cured photodielectric material on each face. At least one hole is photopatterned and etched through the voltage plane element but completely isolated from the voltage plane. Each through hole in the voltage plane element is aligned with a plated through hole in each of the circuit board elements to provide a surface on the voltage plane element communicating with the plated through holes. The voltage plane is laminated between the circuit board elements and the photoimageable material on the voltage plane is fully cured. The surfaces of the voltage plane element communicating with the plated through holes in the circuit board elements are plated with a conducting material to establish a connection between the circuitry on the first and second circuit board elements.
摘要翻译：形成复合层压结构的方法包括提供在其至少一个表面上具有电路的第一和第二电路板元件，并且通孔穿过。提供电压平面元件，其具有在每个面上具有与部分固化的光致电介质材料层相对的表面的至少一个电压平面。至少有一个孔通过电压平面元件进行光刻图案蚀刻，但与电压平面完全隔离。电压平面元件中的每个通孔与每个电路板元件中的电镀通孔对齐，以在与电镀通孔连通的电压平面元件上提供一个表面。电压平面层压在电路板元件和电压平面上的可光成像材料之间完全固化。与电路板元件中的电镀通孔连通的电压平面元件的表面镀有导电材料，以在第一和第二电路板元件之间的电路之间建立连接。

8. 发明授权

US06204456B1 Filling open through holes in a multilayer board 失效
标题翻译：通过多孔板上的孔填充
公开(公告)号：US06204456B1
公开(公告)日：2001-03-20
申请号：US09159938
申请日：1998-09-24
申请人： John M. Lauffer , Voya R. Markovich , Cheryl L. Palomaki , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Cheryl L. Palomaki , William E. Wilson
IPC分类号： H01R909
CPC分类号： H05K3/0094 , H01R12/523 , H05K3/0023 , H05K3/4602 , H05K2201/0209 , H05K2201/09536 , H05K2201/0959 , Y10T29/49165
摘要： Methods of filling apertures, for example, through holes, in substrates are provided. The methods utilize a dielectric film, preferably a photoimageable dielectric film, which is employed to fill the apertures and to form a dielectric film disposed above the substrate at the same time. As a result, the aperture fill material is the same as, and indeed continuous with, the dielectric film which is disposed on the substrate. The method employs the following steps: providing a substrate having apertures; providing a dielectric film disposed on the substrate covering the apertures, reflowing the dielectric film to flow into the apertures and to form a dielectric film adherent to the substrate, to provide a continuous dielectric extending from the dielectric film into the apertures. In certain embodiments, after filling, additional apertures, such as vias, are photoimaged in the dielectric film. Preferably the vias are then metallized, and circuitry formed atop the dielectric film.
摘要翻译：提供了在基板中填充孔的方法，例如通孔。该方法利用电介质膜，优选可光成像的介电膜，其用于填充孔并同时形成设置在基板上方的电介质膜。结果，孔填充材料与设置在基底上的电介质膜相同，实际上是连续的。该方法采用以下步骤：提供具有孔的基底; 提供设置在覆盖所述孔的基板上的电介质膜，回流所述电介质膜流入所述孔中并形成与所述衬底粘附的电介质膜，以提供从所述电介质膜延伸到所述孔中的连续电介质。在某些实施例中，在填充之后，附加的孔，例如通孔，在电介质膜中被光刻。优选地，将通孔金属化，并且在电介质膜的顶部形成电路。

9. 发明授权

US06195883B1 Full additive process with filled plated through holes 失效
标题翻译：完全添加过程，填充电镀通孔
公开(公告)号：US06195883B1
公开(公告)日：2001-03-06
申请号：US09047984
申请日：1998-03-25
申请人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
发明人： Anilkumar C. Bhatt , Voya R. Markovich , Irving Memis , William E. Wilson
IPC分类号： H01K310
CPC分类号： H05K3/0094 , B32B7/04 , H05K1/0306 , H05K1/113 , H05K3/0023 , H05K3/045 , H05K3/184 , H05K3/4053 , H05K3/4069 , H05K3/426 , H05K3/427 , H05K3/4605 , H05K2201/0154 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10734 , H05K2203/0191 , H05K2203/025 , H05K2203/0278 , H05K2203/0338 , H05K2203/0353 , H05K2203/1152 , Y10T29/49126 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.
摘要翻译：一种方法提供在具有填充的电镀通孔的子复合材料上的添加电镀。在电穿孔和填充通孔之后，通过无电沉积实现细线电路。精细线路电路可以通过无地电镀通孔，从而增加纵横比和用于附加部件和布线的可用表面积。

10. 发明授权

US08240031B2 Method of joining a semiconductor device/chip to a printed wiring board 有权
标题翻译：将半导体器件/芯片接合到印刷线路板的方法
公开(公告)号：US08240031B2
公开(公告)日：2012-08-14
申请号：US12837640
申请日：2010-07-16
申请人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
发明人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
IPC分类号： H05K3/30
CPC分类号： H05K3/3436 , H05K1/111 , H05K2201/10378 , Y02P70/613 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/4919
摘要： A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.
摘要翻译：柔性，高密度贴花及其在柔性芯片载体和印刷线路板之间形成可拆卸电互连的方法。柔性贴花在第一表面上具有细间距焊盘，并且在第二表面上具有比微细间距更宽的间距的焊盘，设计成电连接到半导体器件的第一表面上的细间距焊盘和较宽间距第二表面上的焊盘被设计成电连接到印刷线路板等。第一表面上的焊盘通过柔性贴花中的一个或多个绝缘水平导电地连接到第二表面上的焊盘。

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