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1. 发明授权

US5471188A Fast comparator circuit 失效
标题翻译：快速比较电路
公开(公告)号：US5471188A
公开(公告)日：1995-11-28
申请号：US320477
申请日：1994-10-07
申请人： Barbara A. Chappell , Terry I. Chappell , Bruce M. Fleischer , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Bruce M. Fleischer , Stanley E. Schuster
IPC分类号： G06F7/04 , G06F7/02
CPC分类号： G06F7/02
摘要： A fast comparator circuit, including a plurality of first switches operating in parallel. A first data bit from a first data word is input into a first input of each first switch, and a corresponding second data bit from a second data word is respectively input into a second input of each first switch. Each first switch provides a first logic state output when the first data bit matches the corresponding second data bit or a second logic state output when the first data bit does not match the second data bit. A plurality of second switches receive the respective logic state outputs and produce a combined output, indicating an all match or a mismatch, to a third switch combination connected to a first branch node and a second branch node to create a first voltage difference between the first and second branch nodes when an all match output results and a second voltage difference between the first and second branch node when a mismatch output results. A sense amplifier operates to amplify the voltage differentials that develope due to an imbalance caused in the conductance at the two branch nodes.
摘要翻译：一种快速比较器电路，包括并行操作的多个第一开关。来自第一数据字的第一数据位被输入到每个第一开关的第一输入端，并且来自第二数据字的对应的第二数据位分别输入到每个第一开关的第二输入端。当第一数据位与第二数据位匹配时，每个第一开关提供第一逻辑状态输出，或者当第一数据位与第二数据位不匹配时提供第二逻辑状态输出。多个第二开关接收相应的逻辑状态输出并产生指示全部匹配或不匹配的组合输出到连接到第一分支节点和第二分支节点的第三开关组合，以在第一和第二分支节点之间产生第一电压差以及当匹配输出结果时，第二分支节点和第一和第二分支节点之间的第二电压差得到结果。感测放大器用于放大由于在两个分支节点处的电导引起的不平衡而发展的电压差。

2. 发明授权

US5204841A Virtual multi-port RAM 失效
标题翻译：虚拟多端口RAM
公开(公告)号：US5204841A
公开(公告)日：1993-04-20
申请号：US873672
申请日：1992-04-23
申请人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
IPC分类号： G06F12/04 , G06F12/08 , G11C7/10 , G11C8/12 , G11C8/16
CPC分类号： G11C8/16 , G06F12/04 , G11C7/103 , G11C8/12 , G06F12/0855
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译：虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为许多输入触发，自复位，快速循环模块。定时信号从所选择的SRAM块导出，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。每个SRAM块和访问SRAM块的路径中的所有电路块都是输入触发和自复位。多个地址和数据输入锁存器在驱动器处被复用到SRAM段的真实和补码总线，这些总线是自复位的。类似地，所选的SRAM块将数据读出到自复位总线上，并且通过相邻块的释放来将地址和数据输入锁存在用于释放信号的块中，并且这些块都是自复位的。

3. 发明授权

US4845677A Pipelined memory chip structure having improved cycle time 失效
标题翻译：流水线存储芯片结构具有改进的周期时间
公开(公告)号：US4845677A
公开(公告)日：1989-07-04
申请号：US86136
申请日：1987-08-17
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C8/12 , G11C11/401 , G11C11/413
CPC分类号： G11C8/12 , G11C7/1039 , G11C7/12
摘要： A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding and precharging. The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

4. 发明授权

US4843261A Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories 失效
标题翻译：半导体存储器的互补输出，高密度CMOS解码器/驱动电路
公开(公告)号：US4843261A
公开(公告)日：1989-06-27
申请号：US161813
申请日：1988-02-29
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/413 , G11C8/10 , G11C11/408
CPC分类号： G11C8/10
摘要： A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .phi.PC line is included for receiving a .phi.PC precharge clock signal thereon and a .phi.R line is provided for receiving a .phi.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.

5. 发明授权

US5633820A Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability 失效
标题翻译：具有气泡流水线架构的自复位CMOS并行加法器，三轨合并逻辑和增强的可测试性
公开(公告)号：US5633820A
公开(公告)日：1997-05-27
申请号：US463146
申请日：1995-06-05
申请人： Michael P. Beakes , Barbara A. Chappell , Terry I. Chappell , Bruce M. Fleischer , Thao N. Nguyen
发明人： Michael P. Beakes , Barbara A. Chappell , Terry I. Chappell , Bruce M. Fleischer , Thao N. Nguyen
IPC分类号： G06F7/50 , G06F7/508 , H03K19/096
CPC分类号： G06F7/508 , H03K19/0966 , G06F2207/3884 , G06F2207/5063
摘要： A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks. A fast cycle time and minimum delay for each block is achieved by using fast forward amplification of the leading edge of the pulsed input signals followed by quick self-resetting of all nodes back to their standby state.
摘要翻译：并行自复位并行二进制加法器提供高速加减法。该加法器将完全定制的设计方法的优点与自复位互补金属氧化物半导体（CMOS）电路的更高性能潜力相结合。加法器逻辑架构是带有两个位组进行预读，需要六行合并逻辑来计算最高有效位（MSB）的进位。通过将尽可能多的合并块移动到后续行来减少加法器的关键路径上的加载。这使得关键路径中的每个阶段的扇出可以从大约三分之一减小到两分之一。加法器利用气泡流水线电路架构。对于加法器，气泡管段由一排自复位电路块组成。通过使用脉冲输入信号的前沿的快速前向放大，然后快速自复位所有节点回到其待机状态，实现每个块的快速周期时间和最小延迟。

6. 发明授权

US5542067A Virtual multi-port RAM employing multiple accesses during single machine cycle 失效
标题翻译：虚拟多端口RAM在单机周期中采用多次访问
公开(公告)号：US5542067A
公开(公告)日：1996-07-30
申请号：US345328
申请日：1994-11-21
申请人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
IPC分类号： G11C7/10 , G11C8/16 , G05F12/00
CPC分类号： G11C8/16 , G11C7/103 , G11C7/1072
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译：虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为许多输入触发，自复位，快速循环模块。定时信号从所选择的SRAM块导出，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。每个SRAM块和访问SRAM块的路径中的所有电路块都是输入触发和自复位。多个地址和数据输入锁存器在驱动器处被复用到SRAM段的真实和补码总线，这些总线是自复位的。类似地，所选的SRAM块将数据读出到自复位总线上，并且通过相邻块的释放来将地址和数据输入锁存在用于释放信号的块中，并且这些块都是自复位的。

7. 发明授权

US5089726A Fast cycle time clocked amplifier 失效
标题翻译：快速循环时钟放大器
公开(公告)号：US5089726A
公开(公告)日：1992-02-18
申请号：US620512
申请日：1990-11-29
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/413 , G11C11/408 , H03K3/356
CPC分类号： H03K3/356069 , H03K3/356017 , H03K3/356113
摘要： A circuit incorporating a clocked first stage and unlocked second and third stages with amplification for driving capacitance loads with the output nodes each coupling its changed state back to the earlier stages to reset them independent of the clock. The circuit may use complementary metal-oxide semiconductor devices of various gate widths.
摘要翻译：一个并入时钟的第一级的电路和解锁的第二级和第三级，具有用于驱动电容负载的放大的输出节点，每个输出节点将其改变的状态耦合到较早的阶段，以独立于时钟复位它们。电路可以使用各种栅极宽度的互补金属氧化物半导体器件。

8. 发明授权

US5015881A High speed decoding circuit with improved AND gate 失效
标题翻译：具有改进的与门的高速解码电路
公开(公告)号：US5015881A
公开(公告)日：1991-05-14
申请号：US488358
申请日：1990-03-02
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/408 , G11C8/10 , H03K19/017 , H03K19/0948 , H03K19/20 , H03M7/22
CPC分类号： G11C8/10 , H03K19/0948 , H03M7/22
摘要： An AND gate includes first and second opposite-type field effect transistors, each including first and second conduction path terminals and a control electrode. The gate's output terminal is connected, in common, to the second conduction path terminals of the transistors. A first logic input is connected to the first conduction path terminal of the first transistor and a second logic input is connected in common to the control electrode of the first transistor and to the first conduction path terminal of the second transistor. A third logic input is applied to the control electrode of the second transistor. In a standby state prior to the application of logic signals all three logic inputs are in the same state. This assures no conduction of logic signals, while conditioning the gate for rapid selection when logic signals are applied. Subsequently, logic signals are applied to the inputs with the third input being the complement level of the logic signal on the first input. As a result, the circuit's output terminal only provides a high state output if the first and second inputs are in the high state. An erroneous output is avoided in the event of a skew of the inputs due to a clamping acton exerted on the gate's output by the first transistor. A logical decoding circuit using the above described AND circuit enables a one-out-of-32 decode to occur in three stages including a self-contained reset for fast cycle operation.

9. 发明授权

US4998028A High speed CMOS logic device for providing ECL compatible logic levels 失效
标题翻译：高速CMOS逻辑器件，用于提供ECL兼容的逻辑电平
公开(公告)号：US4998028A
公开(公告)日：1991-03-05
申请号：US471155
申请日：1990-01-26
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： H03K3/011 , H03K3/356 , H03K17/14 , H03K19/0185
CPC分类号： H03K3/011 , H03K17/145 , H03K19/018521 , H03K3/356113
摘要： CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit is connected by parallel N channel and P channel devices to serially connected N and P channel devices. The serially connected N and P channel devices are connected across a CMOS power supply with gate connections connected to the logic circuit. The parallel devices provide a regulating feedback current to one of the serially connected P channel and N channel devices during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices. The voltage at the junction of the serially connected P and N channel devices is regulated by each of the parallel connected devices.

10. 发明授权

US4835419A Source-follower emitter-coupled-logic receiver circuit 失效
标题翻译：源极跟随器发射极耦合逻辑接收器电路
公开(公告)号：US4835419A
公开(公告)日：1989-05-30
申请号：US115690
申请日：1987-10-30
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： H03K5/02 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A circuit means for interfacing between small emitter-coupled-logic (ECL) circuit voltage levels and larger field effect transistor (FET) circuits voltage level. The circuit interface means includes a source-follower stage wherein a first transistor device is ratioed relative to a second transistor device, so that a high percentage of an input voltage level signal to the first transistor device appears at a node between the first and second transistor devices, having been level shifted downward by greater than or equal to an n-channel threshold voltage. The percentage is enhanced by applying the complement of the input voltage level signal to the gate of the second transistor device. A gain stage is connected to the source-follower stage and includes third and fourth transistor devices wherein gain is developed by applying the level shifted input signal to the source of the fourth transistor device and the complement of the input signal directly to the gate of the fourth transistor device. A compensation stage for the circuit may also be included.

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