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1. 发明授权

US5356722A Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity 失效
标题翻译：沉积表面灵敏度降低的臭氧/ TEOS氧化硅膜的方法
公开(公告)号：US5356722A
公开(公告)日：1994-10-18
申请号：US896296
申请日：1992-06-10
申请人： Bang Nguyen , Ellie Yieh , Maria Galiano
发明人： Bang Nguyen , Ellie Yieh , Maria Galiano
IPC分类号： H01L21/205 , C23C16/40 , C23C16/452 , H01L21/314 , H01L21/316 , C23C16/00
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/452 , H01L21/02271 , H01L21/02304 , H01L21/3144 , H01L21/31612
摘要： A process for depositing void-free silicon oxide layers over stepped topography comprising depositing a first silicon oxide seed layer which is doped with nitrogen from a plasma of tetraethoxysilane and a nitrogen-containing gas, and depositing thereover a silicon oxide layer from a mixture of tetraethoxysilane, ozone and oxygen at low temperatures to produce a silicon oxide layer having improved properties.
摘要翻译：一种用于在阶梯形地貌上沉积无空隙氧化硅层的方法，包括从四乙氧基硅烷和含氮气体的等离子体中沉积氮掺杂的第一氧化硅晶种层，并从四乙氧基硅烷的混合物沉积氧化硅层，臭氧和氧在低温下产生具有改进性能的氧化硅层。

2. 发明授权

US06218268B1 Two-step borophosphosilicate glass deposition process and related devices and apparatus 失效
标题翻译：两步硼磷硅玻璃沉积工艺及相关设备及装置
公开(公告)号：US06218268B1
公开(公告)日：2001-04-17
申请号：US09076170
申请日：1998-05-05
申请人： Li-Qun Xia , Ellie Yieh , Maria Galiano , Francimar Campana , Shankar Chandran
发明人： Li-Qun Xia , Ellie Yieh , Maria Galiano , Francimar Campana , Shankar Chandran
IPC分类号： H01L2176
CPC分类号： H01L21/02129 , C23C16/045 , C23C16/401 , C23C16/56 , H01L21/022 , H01L21/02271 , H01L21/31625
摘要： A method for forming a BPSG film from a two-step deposition process and related apparatus and devices. A conformal layer of BPSG is deposited on a substrate. A more stable layer of BPSG is deposited at a higher deposition rate over the conformal layer. The method is suitable for filling trenches at least as narrow as 0.06 microns with aspect ratios of at least 5.5:1.
摘要翻译：一种从两步沉积工艺形成BPSG膜的方法及相关设备和装置。 BPSG的保形层沉积在基底上。在保形层上以更高的沉积速率沉积更稳定的BPSG层。该方法适用于填充至少为0.06微米至少为5.5：1的纵横比的沟槽。

3. 发明授权

US06177344B1 BPSG reflow method to reduce thermal budget for next generation device including heating in a steam ambient 有权
标题翻译： BPSG回流方法可降低下一代设备的热预算，包括在蒸汽环境中加热
公开(公告)号：US06177344B1
公开(公告)日：2001-01-23
申请号：US09199911
申请日：1998-11-25
申请人： Li-Qun Xia , Richard A. Conti , Maria Galiano , Ellie Yieh
发明人： Li-Qun Xia , Richard A. Conti , Maria Galiano , Ellie Yieh
IPC分类号： H01L214763
CPC分类号： H01L21/31051 , H01L21/3105 , H01L21/31625
摘要： A multistep method for planarizing a silicon oxide insulating layer such as a deposited borophosphosilicate glass (BPSG) layer. The method includes several different planarization stages. During an initial, pre-planarization stage, a substrate having a BPSG layer deposited over it is loaded into a substrate processing chamber. Then, during a first planarization stage after the pre-planarization stage, oxygen and hydrogen are flowed into the substrate processing chamber to form a steam ambient in said chamber and the substrate is heated in the steam ambient from a first temperature to a second temperature. The first temperature is below a reflow temperature of the BPSG layer and the second temperature is sufficient to reflow the layer. After the substrate is heated to the second temperature during a second planarization stage, the temperature of the substrate and the conditions within the substrate processing chamber are maintained at conditions sufficient to reflow the BPSG layer in the steam ambient. In a more preferred embodiment, the multistep planarization method also includes a third planarization stage, after the second stage. In the third planarization stage, the flow of hydrogen is stopped while the flow of oxygen is maintained, thereby forming an oxygen ambient in the substrate processing chamber. The substrate temperature is maintained in the oxygen ambient at a temperature above the reflow temperature of the BPSG layer. It is believed that this additional step minimizes the amount of moisture incorporated into the reflowed BPSG layer.
摘要翻译：一种用于平坦化氧化硅绝缘层例如沉积的硼磷硅酸盐玻璃（BPSG）层的多步法。该方法包括几个不同的平坦化阶段。在初始预平坦化阶段期间，在其上沉积有BPSG层的衬底被加载到衬底处理室中。然后，在预平坦化阶段之后的第一平坦化阶段期间，氧气和氢气流入基板处理室以在所述室中形成蒸汽环境，并且基板在蒸汽环境中从第一温度加热到第二温度。第一温度低于BPSG层的回流温度，第二温度足以使该层回流。在第二平坦化阶段将衬底加热到第二温度之后，衬底的温度和衬底处理室内的条件保持在足以在蒸汽环境中回流BPSG层的条件。在更优选的实施例中，多级平面化方法还包括在第二级之后的第三平坦化级。在第三平坦化阶段，在保持氧气流的同时停止氢的流动，从而在衬底处理室中形成氧环境。在超过BPSG层的回流温度的温度下，将基板温度保持在氧环境中。据信这个附加步骤使并入回流的BPSG层中的水分量最小化。

4. 发明授权

US06599574B1 Method and apparatus for forming a dielectric film using helium as a carrier gas 失效
标题翻译：使用氦气作为载气形成电介质膜的方法和装置
公开(公告)号：US06599574B1
公开(公告)日：2003-07-29
申请号：US08627631
申请日：1996-04-04
申请人： Ellie Yieh , Paul Gee , Li-Qun Xia , Francimar Campana , Shankar Venkataranan , Dana Tribula , Bang Nguyen
发明人： Ellie Yieh , Paul Gee , Li-Qun Xia , Francimar Campana , Shankar Venkataranan , Dana Tribula , Bang Nguyen
IPC分类号： C23C1600
CPC分类号： H01L21/02129 , C23C16/401 , H01L21/02271 , H01L21/02274 , H01L21/31625 , Y10S438/905 , Y10S438/906
摘要： The present invention relates to the deposition of dielectric layers, and more specifically to a method and apparatus for forming dielectric layers such as borophosphosilicate glass (BPSG) having improved film uniformity, higher deposition rate, superior gap fill/reflow capability, and smoother surface morphology. The method forms a dielectric layer with a process using helium carrier gas that produces substantially less downstream residue than conventional methods and apparatus, thereby reducing the need for chamber cleaning and increasing throughput of processed wafers. The present invention utilizes helium instead of nitrogen as carrier gas in a process for forming a dielectric layer such as BPSG to provide various unexpected benefits. According to one aspect, the present invention forms a dielectric film on a substrate, and prolongs a period between chamber cleanings in a system by using helium which produces substantially less downstream and upstream residue than a process using nitrogen. The method includes introducing a process gas containing silicon, oxygen, and first dopant atoms into the chamber; using helium as the carrier gas in the system; and processing more substrates between cleanings than a process using nitrogen as carrier gas. A further aspect of the invention includes annealing the dielectric films formed on the substrates at a lower temperature than required by the process using nitrogen as carrier gas.
摘要翻译：本发明涉及电介质层的沉积，更具体地涉及一种用于形成介电层的方法和装置，例如具有改进的膜均匀性，较高沉积速率，优异的间隙填充/回流能力和更平滑的表面形态的硼磷硅酸盐玻璃（BPSG）。该方法形成具有使用氦载气的方法的电介质层，其产生比常规方法和设备基本上更少的下游残留物，从而减少对室清洁的需要并增加处理的晶片的生产量。本发明在形成诸如BPSG的介电层的工艺中使用氦代替氮作为载气，以提供各种意想不到的好处。根据一个方面，本发明在衬底上形成介电膜，并且通过使用产生比使用氮的方法显着更少的下游和上游残留物的氦来延长系统中的室清洁之间的时间。该方法包括将含有硅，氧和第一掺杂剂原子的工艺气体引入室中; 使用氦气作为系统中的载气; 并且在清洗之前处理比使用氮气作为载气的工艺更多的衬底。本发明的另一方面包括在比使用氮作为载气的方法所要求的温度更低的温度下退火形成在基板上的电介质膜。

5. 发明授权

US6099647A Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films 有权
标题翻译：使用掺杂氧化硅膜形成超浅掺杂区域的方法和装置
公开(公告)号：US6099647A
公开(公告)日：2000-08-08
申请号：US409763
申请日：1999-09-30
申请人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
发明人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
IPC分类号： C23C16/40 , C23C16/44 , C23C16/509 , C23C16/52 , H01L21/225 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/762 , C23C16/00
CPC分类号： C23C16/401 , C23C16/402 , C23C16/4405 , C23C16/4412 , C23C16/5096 , C23C16/52 , H01L21/02129 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02301 , H01L21/02312 , H01L21/02315 , H01L21/0234 , H01L21/02362 , H01L21/2255 , H01L21/31625 , H01L21/76237 , H01L29/66575
摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
摘要翻译：本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

6. 发明授权

US5994209A Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films 失效
公开(公告)号：US5994209A
公开(公告)日：1999-11-30
申请号：US748094
申请日：1996-11-13
申请人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
发明人： Ellie Yieh , Li-Qun Xia , Paul Gee , Bang Nguyen
IPC分类号： C23C16/40 , C23C16/44 , C23C16/509 , C23C16/52 , H01L21/225 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/762 , H01L21/24 , H01L21/40
CPC分类号： C23C16/401 , C23C16/402 , C23C16/4405 , C23C16/4412 , C23C16/5096 , C23C16/52 , H01L21/02129 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02301 , H01L21/02312 , H01L21/02315 , H01L21/0234 , H01L21/02362 , H01L21/2255 , H01L21/31625 , H01L21/76237 , H01L29/66575
摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

7. 发明授权

US6121164A Method for forming low compressive stress fluorinated ozone/TEOS oxide film 失效
标题翻译：形成低压应力氟化臭氧/ TEOS氧化膜的方法
公开(公告)号：US6121164A
公开(公告)日：2000-09-19
申请号：US957058
申请日：1997-10-24
申请人： Ellie Yieh , Xin Zhang , Bang Nguyen , Stuardo Robles , Peter Lee
发明人： Ellie Yieh , Xin Zhang , Bang Nguyen , Stuardo Robles , Peter Lee
IPC分类号： C23C16/40 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02131 , C23C16/402 , H01L21/02274 , H01L21/02362 , H01L21/31629
摘要： A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5.times.10.sup.8 dynes/cm.sup.2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.
摘要翻译：用于形成压电应力小于约-5×10 8达因/ cm 2的卤素掺杂氧化硅膜，优选氟化硅玻璃（FSG）膜的方法和装置。在一个具体的实施方案中，FSG膜通过在大约60-650托之间的压力下的低于大气压的CVD热处理形成。除了具有低介电常数和良好的间隙填充能力之外，相对薄的膜具有低的压缩应力，并且特别适合用作金属间（IMD）层。

8. 发明申请

US20170069488A1 METHOD AND SYSTEM FOR THREE-DIMENSIONAL (3D) STRUCTURE FILL 审中-公开
标题翻译：三维（3D）结构填充的方法和系统
公开(公告)号：US20170069488A1
公开(公告)日：2017-03-09
申请号：US15356475
申请日：2016-11-18
申请人： Ellie Yieh , Ludovic Godet , Srinivas Nemani , Er-Xuan Ping , Gary Dickerson
发明人： Ellie Yieh , Ludovic Godet , Srinivas Nemani , Er-Xuan Ping , Gary Dickerson
IPC分类号： H01L21/02 , H01L21/285 , H01L21/3213 , C23C14/02 , C23C16/455 , C23C16/02 , C23C16/04 , H01J37/32 , C23C16/50 , H01L21/311 , C23C14/04
CPC分类号： H01L21/02271 , C23C14/021 , C23C14/046 , C23C16/0227 , C23C16/045 , C23C16/45544 , C23C16/50 , H01J37/32009 , H01J2237/334 , H01L21/02266 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/2855 , H01L21/28556 , H01L21/31116 , H01L21/32136 , H01L21/67017 , H01L21/67213 , H01L21/76224
摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.
摘要翻译：实施例包括3D结构填充的方法和系统。在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。材料沉积在沟槽中。材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

9. 发明授权

US08741775B2 Method of patterning a low-K dielectric film 有权
标题翻译：图案化低K电介质膜的方法
公开(公告)号：US08741775B2
公开(公告)日：2014-06-03
申请号：US13187224
申请日：2011-07-20
申请人： Srinivas D. Nemani , Yifeng Zhou , Dmitry Lubomirsky , Ellie Yieh
发明人： Srinivas D. Nemani , Yifeng Zhou , Dmitry Lubomirsky , Ellie Yieh
IPC分类号： H01L21/3105
CPC分类号： H01L21/3105 , H01L21/02126 , H01L21/02203 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。例如，一种方法包括在低k电介质层之上形成和图案化掩模层，低k电介质层设置在衬底之上。低等离子体介质层的露出部分用等离子体工艺进行改性。低k电介质层的修改部分被选择性地去除低k电介质层的掩模层和未修饰部分。

10. 发明申请

US20070132054A1 MEMORY CELL HAVING STRESSED LAYERS 失效
标题翻译：具有压力层的记忆体
公开(公告)号：US20070132054A1
公开(公告)日：2007-06-14
申请号：US11609851
申请日：2006-12-12
申请人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
发明人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
IPC分类号： H01L29/00
CPC分类号： H01L29/7846 , H01L27/105 , H01L27/1052 , H01L29/66825 , H01L29/7883
摘要： A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.
摘要翻译：存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底，其在沟道周围形成源极和漏极。通道上的层叠层包括（i）隧道氧化物层，（ii）浮动栅极，（iii）栅极间电介质和（iv）控制栅极。源极和漏极上的多晶硅层。覆盖层叠层的覆盖层包括间隔层和预金属沉积层。可选地，使用触点来接触源极，漏极和硅化物层中的每一个，并且每个都具有暴露部分。围绕n掺杂区域提供浅的隔离沟槽，沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。

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