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1. 发明申请

US20050048742A1 Multiple grow-etch cyclic surface treatment for substrate preparation 审中-公开
标题翻译：用于底物制备的多次生长蚀刻循环表面处理
公开(公告)号：US20050048742A1
公开(公告)日：2005-03-03
申请号：US10647534
申请日：2003-08-26
申请人： Anthony Dip , Pradip Roy , Raymond Joe
发明人： Anthony Dip , Pradip Roy , Raymond Joe
IPC分类号： H01L21/28 , H01L21/306 , H01L21/302 , H01L21/322 , H01L21/461
CPC分类号： H01L21/28238 , H01L21/02049 , H01L21/02052 , H01L21/28255
摘要： This invention provides a method for modifying the surface properties of a Si or Si alloy substrate by performing repeated etch-grow cycles of thermal oxide to yield a more defect free substrate with a more uniform nucleating surface which provides an improved interface for dielectric formation. Additionally, this method of processing does not expose the substrate to ambient atmosphere and preserves the improved surface until subsequent processing steps are performed.
摘要翻译：本发明提供了一种通过进行热氧化物的重复蚀刻生长循环来改善Si或Si合金衬底的表面性质的方法，以产生具有更均匀的成核表面的更无缺陷的衬底，其提供用于电介质形成的改进的界面。此外，这种处理方法不会使衬底暴露于环境大气中并保留改进的表面，直到执行后续的处理步骤。

2. 发明申请

US20050199877A1 Silicon germanium surface layer for high-k dielectric integration 有权
标题翻译：硅锗表面层用于高k电介质集成
公开(公告)号：US20050199877A1
公开(公告)日：2005-09-15
申请号：US10797876
申请日：2004-03-10
申请人： Anthony Dip , Pradip Roy , Sanjeev Kaushal , Allen Leith , Seungho Oh , Raymond Joe
发明人： Anthony Dip , Pradip Roy , Sanjeev Kaushal , Allen Leith , Seungho Oh , Raymond Joe
IPC分类号： H01L21/28 , H01L21/316 , H01L21/318 , H01L29/51 , H01L29/12 , H01L21/36 , H01L21/3205
CPC分类号： H01L21/31604 , H01L21/02142 , H01L21/0217 , H01L21/02175 , H01L21/02318 , H01L21/02323 , H01L21/02337 , H01L21/02362 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/3185 , Y10T29/41
摘要： A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.
摘要翻译：一种使用硅锗（SiGe）表面层将高k电介质层集成到半导体器件中的方法。该方法在衬底上形成SiGe表面层，并在SiGe表面层上沉积高k电介质层。在高k电介质层的沉积和沉积高k电介质层之间的退火工艺中的一个或两个期间，形成位于高k电介质层和SiGe表面层的未反应部分之间的氧化物层。该方法还包括在高k电介质层上形成电极层。

3. 发明申请

US20050199872A1 Silicon-germanium thin layer semiconductor structure with variable silicon-germanium composition and method of fabrication 审中-公开
标题翻译：具有可变硅 - 锗组成的硅 - 锗薄层半导体结构及其制造方法
公开(公告)号：US20050199872A1
公开(公告)日：2005-09-15
申请号：US10797425
申请日：2004-03-10
申请人： Pradip Roy , Anthony Dip , Allen Leith , Seungho Oh
发明人： Pradip Roy , Anthony Dip , Allen Leith , Seungho Oh
IPC分类号： H01L21/00 , H01L21/20 , H01L21/205 , H01L21/28 , H01L29/161 , H01L29/49 , H01L29/06
CPC分类号： H01L21/67109 , H01L21/0237 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/2807 , H01L29/161
摘要： A SiGe thin layer semiconductor structure containing a substrate having a dielectric layer, a variable composition SixGe1-x layer on dielectric layer, and a Si cap layer on the variable composition SixGe1-x layer. The variable composition SixGe1-x layer can contain a SixGe1-x layer with a graded Ge content or a plurality of SixGe1-x sub-layers each with different Ge content. In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate having a dielectric layer, a Si-containing seed layer on the dielectric layer, a variable composition SixGe1-x layer on the seed layer, and a Si cap layer on the variable composition SixGe1-x layer. A method and processing tool for fabricating the SiGe thin layer semiconductor structure are also provided.
摘要翻译： SiGe薄层半导体结构，其包含在电介质层上具有电介质层，可变成分Si x 1 Ge 1-x层的衬底和可变组件上的Si覆盖层组合物Si 1 x 1-x <＆gt;层。可变成分Si x 1 Ge 1-x层可以含有Si x N 1 Ge 1-x层，其中a 分级的Ge含量或多个具有不同Ge含量的Si x 1 Ge 1-x N sub子层。在本发明的一个实施例中，SiGe薄层半导体结构包含具有电介质层的半导体衬底，介电层上的含Si种子层，可变成分Si x Si -x 层，以及可变成分Si x 1 Ge 1-x层上的Si覆盖层。还提供了一种用于制造SiGe薄层半导体结构的方法和处理工具。

4. 发明申请

US20050221001A1 Method for extending time between chamber cleaning processes 有权
标题翻译：在室清洁过程之间延长时间的方法
公开(公告)号：US20050221001A1
公开(公告)日：2005-10-06
申请号：US10814713
申请日：2004-03-31
申请人： Raymond Joe , John Gumpher , Anthony Dip
发明人： Raymond Joe , John Gumpher , Anthony Dip
IPC分类号： C23C16/34 , C23C16/44 , H01L21/318 , C23C16/00 , B32B9/00
CPC分类号： C23C16/4404 , H01L21/3185
摘要： A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.
摘要翻译：一种用于在处理系统的处理室中延长室清洁过程之间的时间的方法。在处理室中的腔室部件上形成颗粒减少膜，以减少衬底处理期间处理室中的颗粒形成，至少一个衬底被引入到处理室中，在处理室中执行制造工艺，从处理室移除至少一个基板。颗粒减少膜可以沉积在清洁室部件上或者形成在室部件上的材料沉积物上。或者，可以通过化学改变室内部件上的材料沉积物的至少一部分来形成颗粒减少膜。减少颗粒的膜可以在每个制造过程之后形成，或者在多个制造过程之后以选定的间隔形成。

5. 发明授权

US07165011B1 Built-in self test for a thermal processing system 有权
标题翻译：热处理系统内置自检
公开(公告)号：US07165011B1
公开(公告)日：2007-01-16
申请号：US11217230
申请日：2005-09-01
申请人： Sanjeev Kaushal , Pradeep Pandey , Kenji Sugishima , Anthony Dip , David Smith , Raymond Joe , Sundar Gandhi
发明人： Sanjeev Kaushal , Pradeep Pandey , Kenji Sugishima , Anthony Dip , David Smith , Raymond Joe , Sundar Gandhi
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： H01L22/10 , G05B23/0254 , H01L21/67248
摘要： A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response for the processing chamber during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BIST table.
摘要翻译：一种使用内置自检（BIST）表实时监测热处理系统的方法，其包括将多个晶片定位在热处理系统中的处理室中; 执行实时动态模型以在处理时间期间为处理室生成预测的动态过程响应; 创建第一个测量动态过程响应; 使用预测的动态过程响应和测量的动态过程响应之间的差来确定动态估计误差; 以及将动态估计误差与由BIST表中的一个或多个规则建立的操作阈值进行比较。

6. 发明授权

US07022192B2 Semiconductor wafer susceptor 失效
标题翻译：半导体晶圆基座
公开(公告)号：US07022192B2
公开(公告)日：2006-04-04
申请号：US10233483
申请日：2002-09-04
申请人： Anthony Dip , Takanori Saito , Raymond Joe
发明人： Anthony Dip , Takanori Saito , Raymond Joe
IPC分类号： H01L21/00 , C23C16/00
CPC分类号： H01L21/67309 , Y10S206/832
摘要： A semiconductor wafer susceptor for batch substrate processing. The susceptor includes a central region in a primary plane and a plurality of flat annular extensions extending below the central region in a secondary plane. The primary and secondary planes are parallel to each other. An edge of the substrate overhangs the central region allowing no contact of the susceptor with the substrate edge.
摘要翻译：用于批量衬底加工的半导体晶片基座。基座包括主平面中的中心区域和在次平面内在中心区域下方延伸的多个平的环形延伸部。主平面和次平面彼此平行。衬底的边缘突出中心区域，允许基座与衬底边缘不接触。

7. 发明申请

US20050217799A1 Wafer heater assembly 审中-公开
标题翻译：晶圆加热器总成
公开(公告)号：US20050217799A1
公开(公告)日：2005-10-06
申请号：US10813119
申请日：2004-03-31
申请人： David O'Meara , Gerrit Leusink , Stephen Cabral , Anthony Dip , Cory Wajda , Raymond Joe
发明人： David O'Meara , Gerrit Leusink , Stephen Cabral , Anthony Dip , Cory Wajda , Raymond Joe
IPC分类号： C23F1/00 , H01L21/00
CPC分类号： H01L21/67109 , H01J2237/2001
摘要： A wafer heating assembly is described having a unique heater element for use in a single wafer processing systems. The heating unit includes a carbon wire element encased in a quartz sheath. The heating unit is as contamination-free as the quartz, which permits direct contact to the wafer. The mechanical flexibility of the carbon ‘wire’ or ‘braided’ structure permits a coil configuration, which permits independent heater zone control across the wafer. The multiple independent heater zones across the wafer can permit temperature gradients to adjust film growth/deposition uniformity and rapid thermal adjustments with film uniformity superior to conventional single wafer systems and with minimum to no wafer warping. The low thermal mass permits a fast thermal response that enables a pulsed or digital thermal process that results in layer-by-layer film formation for improved thin film control.
摘要翻译：描述了具有用于单个晶片处理系统的唯一加热器元件的晶片加热组件。加热单元包括封装在石英鞘中的碳线元件。加热单元与石英无污染，允许直接接触晶片。碳线或“编织”结构的机械灵活性允许线圈构造，其允许跨晶片的独立加热器区域控制。跨晶片的多个独立的加热器区域可以允许温度梯度调节膜生长/沉积均匀性和快速的热调节，其膜均匀性优于常规单晶片系统，并且最小至无晶片翘曲。低热质量允许快速的热响应，其实现脉冲或数字热处理，其导致逐层成膜以改善薄膜控制。

8. 发明授权

US06799940B2 Removable semiconductor wafer susceptor 失效
标题翻译：可移动半导体晶圆基座
公开(公告)号：US06799940B2
公开(公告)日：2004-10-05
申请号：US10310141
申请日：2002-12-05
申请人： Raymond Joe , Anthony Dip
发明人： Raymond Joe , Anthony Dip
IPC分类号： B65G4907
CPC分类号： H01L21/68735 , H01L21/67109 , H01L21/67309 , H01L21/67346 , Y10S414/135 , Y10S414/137
摘要： A removable semiconductor wafer susceptor used for supporting a substrate during batch processing. The susceptor includes a flat circular central plane with a predetermined outer diameter. The susceptor is sized to fit within an inner diameter formed from wafer support ledges of a wafer transport container. The susceptor includes edges that are chamfered and rounded to lessen stress concentration at the edges. The susceptor is transported through processing by a sieving action of transport automation.
摘要翻译：用于在批量处理期间支撑基板的可移除的半导体晶片基座。基座包括具有预定外径的平圆形中心平面。基座的尺寸设计成适合于由晶片运输容器的晶片支撑壁架形成的内径。基座包括倒角和倒圆的边缘，以减少边缘处的应力集中。感受器通过运输自动化的筛选动作运输。

9. 发明授权

US07737051B2 Silicon germanium surface layer for high-k dielectric integration 有权
标题翻译：硅锗表面层用于高k电介质集成
公开(公告)号：US07737051B2
公开(公告)日：2010-06-15
申请号：US10797876
申请日：2004-03-10
申请人： Anthony Dip , Pradip K. Roy , Sanjeev Kaushal , Allen J. Leith , Seungho Oh , Raymond Joe
发明人： Anthony Dip , Pradip K. Roy , Sanjeev Kaushal , Allen J. Leith , Seungho Oh , Raymond Joe
IPC分类号： H01L21/36
CPC分类号： H01L21/31604 , H01L21/02142 , H01L21/0217 , H01L21/02175 , H01L21/02318 , H01L21/02323 , H01L21/02337 , H01L21/02362 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/3185 , Y10T29/41
摘要： A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.
摘要翻译：一种使用硅锗（SiGe）表面层将高k电介质层集成到半导体器件中的方法。该方法在衬底上形成SiGe表面层，并在SiGe表面层上沉积高k电介质层。在高k电介质层的沉积和沉积高k电介质层之间的退火工艺中的一个或两个期间，形成位于高k电介质层和SiGe表面层的未反应部分之间的氧化物层。该方法还包括在高k电介质层上形成电极层。

10. 发明授权

US07604841B2 Method for extending time between chamber cleaning processes 有权
标题翻译：在室清洁过程之间延长时间的方法
公开(公告)号：US07604841B2
公开(公告)日：2009-10-20
申请号：US10814713
申请日：2004-03-31
申请人： Raymond Joe , John Gumpher , Anthony Dip
发明人： Raymond Joe , John Gumpher , Anthony Dip
IPC分类号： C23C16/30
CPC分类号： C23C16/4404 , H01L21/3185
摘要： A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.
摘要翻译：一种用于在处理系统的处理室中延长室清洁过程之间的时间的方法。在处理室中的腔室部件上形成颗粒减少膜，以减少衬底处理期间处理室中的颗粒形成，至少一个衬底被引入到处理室中，在处理室中执行制造工艺，从处理室移除至少一个基板。颗粒减少膜可以沉积在清洁室部件上或者形成在室部件上的材料沉积物上。或者，可以通过化学改变室内部件上的材料沉积物的至少一部分来形成颗粒减少膜。减少颗粒的膜可以在每个制造过程之后形成，或者在多个制造过程之后以选定的间隔形成。

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