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1. 发明授权

US5492858A Shallow trench isolation process for high aspect ratio trenches 失效
标题翻译：用于高纵横比沟槽的浅沟槽隔离工艺
公开(公告)号：US5492858A
公开(公告)日：1996-02-20
申请号：US230180
申请日：1994-04-20
申请人： Amitava Bose , Marion M. Garver , Andre I. Nasr , Steven S. Cooperman
发明人： Amitava Bose , Marion M. Garver , Andre I. Nasr , Steven S. Cooperman
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.
摘要翻译：公开了在采用浅沟槽隔离技术的集成电路制造中平面化硅晶片的表面的方法。在沟槽和有源区域台面共形涂覆有氧化硅层之前，蚀刻的沟槽首先被涂覆有氮化硅保护衬垫。然后对共形氧化物进行蒸汽退火以使保形氧化物致密化，然后将硅晶片的表面蚀刻并抛光回到有源区域台面的顶部，以形成基本平坦的表面。

2. 发明授权

US5494857A Chemical mechanical planarization of shallow trenches in semiconductor substrates 失效
标题翻译：半导体衬底中浅沟槽的化学机械平面化
公开(公告)号：US5494857A
公开(公告)日：1996-02-27
申请号：US98533
申请日：1993-07-28
申请人： Steven S. Cooperman , Andre I. Nasr
发明人： Steven S. Cooperman , Andre I. Nasr
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/304 , H01L21/76
CPC分类号： H01L21/31053 , H01L21/31055 , H01L21/76229
摘要： A new method for planarization of shallow trenches is presented. Shallow trenches are patterned into a semiconductor substrate that has been coated with a layer of silicon nitride. A conformal coating of oxide is deposited onto the wafer to fill the trenches. A thin layer of etch-stop silicon and a second layer of oxide are then deposited. The second layer of oxide is patterned with a filler mask using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.
摘要翻译：提出了一种新的浅沟槽平面化方法。浅沟槽被图案化成已经涂覆有氮化硅层的半导体衬底。将氧化物的保形涂层沉积在晶片上以填充沟槽。然后沉积薄层的蚀刻停止硅和第二层氧化物。使用常规的光刻技术，用填充掩模对第二层氧化物进行图案化，并蚀刻到硅蚀刻停止层，在沿着侧壁的沟槽和氧化物间隔物上方的凹陷中留下一层氧化物。然后使用化学机械抛光将氧化物抛光回氮化硅。该工艺提供优异的全局平面度，在不同尺寸和密度的有源区域上的氮化硅厚度的最小变化以及对芯片设计的相对不敏感性。

3. 发明授权

US5346584A Planarization process for IC trench isolation using oxidized polysilicon filler 失效
标题翻译：使用氧化多晶硅填料的IC沟槽隔离的平面化处理
公开(公告)号：US5346584A
公开(公告)日：1994-09-13
申请号：US98164
申请日：1993-07-28
申请人： Andre I. Nasr , Steven S. Cooperman
发明人： Andre I. Nasr , Steven S. Cooperman
IPC分类号： H01L21/763 , H01L21/306 , H01L21/304
CPC分类号： H01L21/763
摘要： Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.
摘要翻译：公开了在采用沟槽隔离技术的集成电路制造中对硅晶片的表面进行平面化的方法。半导体衬底上的沟槽和有源区域共形地涂覆有一层氧化硅。然后将一层图案化多晶硅沉积在氧化物的顶部上并被蚀刻以在沟槽上方的凹陷中产生填充块。接下来，将多晶硅退火，从而用膨胀的氧化物块填充沟槽。然后将所得的相对平坦的表面抛光回氮化物盖，从而在所有沟槽和有源区域尺寸上产生高度的平面度。

4. 发明授权

US07470562B2 Methods of forming field effect transistors using disposable aluminum oxide spacers 有权
标题翻译：使用一次性氧化铝间隔物形成场效应晶体管的方法
公开(公告)号：US07470562B2
公开(公告)日：2008-12-30
申请号：US11268132
申请日：2005-11-07
申请人： Jong Pyo Kim , Andre I. Nasr
发明人： Jong Pyo Kim , Andre I. Nasr
IPC分类号： H01L21/16 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a field effect transistor by forming a gate electrode on a semiconductor substrate and forming aluminum oxide spacers on sidewalls of the gate electrode. Source and drain region dopants of first conductivity type are implanted into the semiconductor substrate using the aluminum oxide spacers as an implant mask. Thereafter, the aluminum oxide spacers are selectively removed by exposing them to tetramethyl ammonium hydroxide (TMAH). The step of selectively removing the aluminum oxide spacers may include exposing the aluminum oxide spacers to tetramethyl ammonium hydroxide having a temperature of about 80° C.
摘要翻译：通过在半导体衬底上形成栅电极并在栅电极的侧壁上形成氧化铝间隔物来形成场效应晶体管的方法。使用氧化铝间隔物作为植入物掩模将第一导电类型的源区和漏区掺杂剂注入到半导体衬底中。此后，通过将氧化铝间隔物暴露于四甲基氢氧化铵（TMAH）中来选择性地除去氧化铝间隔物。选择性去除氧化铝间隔物的步骤可以包括将氧化铝间隔物暴露于温度为约80℃的四甲基氢氧化铵

5. 发明授权

US5563096A Semiconductor device fabrication with planar gate interconnect surface 失效
标题翻译：具有平面栅极互连表面的半导体器件制造
公开(公告)号：US5563096A
公开(公告)日：1996-10-08
申请号：US560853
申请日：1995-11-20
申请人： Andre I. Nasr
发明人： Andre I. Nasr
IPC分类号： H01L21/28 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28123 , H01L21/7684
摘要： In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided. A silicide is formed over the top of the gate interconnect and over the diffusion areas.
摘要翻译：根据本发明的原理，提供了一种用于半导体器件制造的新工艺。所公开的方法包括在硅晶片的表面上形成场隔离区域，并且在场隔离区域之间选择性地形成栅极氧化物区域。栅极互连材料沉积在场隔离区域和栅极氧化物区域上。在栅极互连材料的顶部上形成平坦的表面。该平坦化步骤可以通过化学机械抛光或一些其它方便的方法例如抗蚀剂回蚀来实现。在栅极互连材料的平坦化之后，在平坦表面上沉积均匀的厚度的光致抗蚀剂。使用光刻在平面表面上形成栅极互连蚀刻图案，并且蚀刻栅极互连材料以匹配栅极互连图案并且去除光致抗蚀剂。提供侧壁间隔件。在栅极互连的顶部和扩散区域之上形成硅化物。

6. 发明授权

US4912061A Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer 失效
标题翻译：使用一次性氮化硅间隔物形成水银自对准金属氧化物半导体器件的方法
公开(公告)号：US4912061A
公开(公告)日：1990-03-27
申请号：US176837
申请日：1988-04-04
申请人： Andre I. Nasr
发明人： Andre I. Nasr
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/66575 , H01L21/823814 , H01L29/665 , H01L29/6656 , Y10S148/019 , Y10S148/147
摘要： A method of fabricating a SALICIDED self aligned metal oxide semiconductor device using a disposable silicon nitride spacer, metal silicide and a single implant step for the source, drain and gate regions is disclosed. The fabrication of the device is accomplished in seven major steps: First, on a substrate having an oxide layer, an undoped polysilicon layer defining the gate region is deposited. Second, an oxide layer is grown and then a silicon nitride layer is deposited. Third, the oxide and the silicon nitride layers are selectively etched, leaving the oxide and the nitride layers on the walls of the polysilicon gate region. Fourth, a cobalt layer is deposited on the wafer and processed to form cobalt silicide, after which the cobalt that did not come in contact with the silicon or the polysilicon gate region is removed. Fifth, the nitride layer on the walls of the gate region is removed. Sixth, a single ion implant step is used to form the N-channel Transistors of the device. Seventh, a single ion implant step is used to form the P-channel transistor of the device.
摘要翻译：公开了一种使用一次性氮化硅间隔物，金属硅化物和用于源极，漏极和栅极区域的单个注入步骤制造SALICIDED自对准金属氧化物半导体器件的方法。器件的制造通过七个主要步骤完成：首先，在具有氧化物层的衬底上沉积限定栅极区域的未掺杂多晶硅层。其次，生长氧化物层，然后沉积氮化硅层。第三，选择性地蚀刻氧化物和氮化硅层，在多晶硅栅极区域的壁上留下氧化物和氮化物层。第四，将钴层沉积在晶片上并加工以形成硅化钴，之后除去未与硅或多晶硅栅极区接触的钴。第五，去除栅极区域的壁上的氮化物层。第六，使用单个离子注入步骤来形成器件的N沟道晶体管。第七，使用单个离子注入步骤来形成器件的P沟道晶体管。

7. 发明授权

US06534351B2 Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices 失效
公开(公告)号：US06534351B2
公开(公告)日：2003-03-18
申请号：US09811730
申请日：2001-03-19
申请人： K. Paul Muller , Andre I. Nasr
发明人： K. Paul Muller , Andre I. Nasr
IPC分类号： H01L21338
CPC分类号： H01L29/66553 , H01L21/28114 , H01L21/28518 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance. A method for making the gate-controlled device includes forming the source/drain regions and shallow LDD extensions before deposition of the gate. This advantageously allows high-k dielectrics to be used in the device with reduced temperature stability. Further, the method may be performed in a self-aligned manner, which allows for dopant dose reduction with a commensurate reduction in junction capacitance.

8. 发明授权

US06825545B2 On chip decap trench capacitor (DTC) for ultra high performance silicon on insulator (SOI) systems microprocessors 失效
标题翻译：用于超高性能绝缘体上硅（SOI）系统微处理器的片上贴片沟槽电容器（DTC）
公开(公告)号：US06825545B2
公开(公告)日：2004-11-30
申请号：US10249386
申请日：2003-04-03
申请人： Andre I. Nasr
发明人： Andre I. Nasr
IPC分类号： H01L2994
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1203 , H01L29/945
摘要： A semiconductor method integrates a DTC on SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the silicon area used. The DTC for SOI devices comprises a buried oxide layer on a silicon substrate with a silicon layer over the buried oxide layer. Shallow trench insulation extends to the buried oxide layer in the silicon layer. A first trench is formed in the shallow trench insulation and extends through the buried oxide layer into the silicon substrate. The first trench has formed on the walls thereof an oxide insulating layer and is then filled with polysilicon to form the DTC. A second trench is formed in the silicon layer adjacent to the first trench and extends through the buried oxide layer into the silicon substrate. The second trench is filled with polysilicon and forms the substrate contact for the DTC.
摘要翻译：半导体方法将SOI上的DTC集成在一起，以减少所使用的硅面积，实现低噪声的鲁棒电路设计。用于SOI器件的DTC包括在硅衬底上的掩埋氧化物层，在掩埋氧化物层上方具有硅层。浅沟槽绝缘体延伸到硅层中的掩埋氧化物层。第一沟槽形成在浅沟槽绝缘体中并且延伸穿过掩埋氧化物层进入硅衬底。第一沟槽在其壁上形成氧化物绝缘层，然后用多晶硅填充以形成DTC。在与第一沟槽相邻的硅层中形成第二沟槽，并延伸穿过掩埋氧化物层进入硅衬底。第二沟槽填充有多晶硅并形成DTC的衬底接触。

9. 发明授权

US5266156A Methods of forming a local interconnect and a high resistor polysilicon load by reacting cobalt with polysilicon 失效
标题翻译：通过钴与多晶硅反应形成局部互连和高电阻多晶硅负载的方法
公开(公告)号：US5266156A
公开(公告)日：1993-11-30
申请号：US904389
申请日：1992-06-25
申请人： Andre I. Nasr
发明人： Andre I. Nasr
IPC分类号： H01L21/02 , H01L21/768 , H01L27/11 , H01L21/312
CPC分类号： H01L28/24 , H01L21/76889 , H01L21/76895 , H01L27/1112 , Y10S148/106
摘要： Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi.sub.2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi.sub.2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.
摘要翻译：公开了形成局部互连和高电阻多晶硅负载的方法。局部互连通过在部分制造的半导体晶片中在CoSi 2上沉积多晶硅层而形成。然后用钴涂覆多晶硅并退火以形成第二层CoSi 2。可以通过在施加多晶硅层之前沉积和图案化氧化物层以形成接触窗口来扩展该方法以形成高电阻多晶硅负载。另外的氧化物层沉积在多晶硅上并在施加钴层之前被图案化以限定产生电阻器负载的区域。

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