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1. 发明授权

US5492858A Shallow trench isolation process for high aspect ratio trenches 失效
标题翻译：用于高纵横比沟槽的浅沟槽隔离工艺
公开(公告)号：US5492858A
公开(公告)日：1996-02-20
申请号：US230180
申请日：1994-04-20
申请人： Amitava Bose , Marion M. Garver , Andre I. Nasr , Steven S. Cooperman
发明人： Amitava Bose , Marion M. Garver , Andre I. Nasr , Steven S. Cooperman
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.
摘要翻译：公开了在采用浅沟槽隔离技术的集成电路制造中平面化硅晶片的表面的方法。在沟槽和有源区域台面共形涂覆有氧化硅层之前，蚀刻的沟槽首先被涂覆有氮化硅保护衬垫。然后对共形氧化物进行蒸汽退火以使保形氧化物致密化，然后将硅晶片的表面蚀刻并抛光回到有源区域台面的顶部，以形成基本平坦的表面。

2. 发明授权

US5494857A Chemical mechanical planarization of shallow trenches in semiconductor substrates 失效
标题翻译：半导体衬底中浅沟槽的化学机械平面化
公开(公告)号：US5494857A
公开(公告)日：1996-02-27
申请号：US98533
申请日：1993-07-28
申请人： Steven S. Cooperman , Andre I. Nasr
发明人： Steven S. Cooperman , Andre I. Nasr
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/304 , H01L21/76
CPC分类号： H01L21/31053 , H01L21/31055 , H01L21/76229
摘要： A new method for planarization of shallow trenches is presented. Shallow trenches are patterned into a semiconductor substrate that has been coated with a layer of silicon nitride. A conformal coating of oxide is deposited onto the wafer to fill the trenches. A thin layer of etch-stop silicon and a second layer of oxide are then deposited. The second layer of oxide is patterned with a filler mask using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.
摘要翻译：提出了一种新的浅沟槽平面化方法。浅沟槽被图案化成已经涂覆有氮化硅层的半导体衬底。将氧化物的保形涂层沉积在晶片上以填充沟槽。然后沉积薄层的蚀刻停止硅和第二层氧化物。使用常规的光刻技术，用填充掩模对第二层氧化物进行图案化，并蚀刻到硅蚀刻停止层，在沿着侧壁的沟槽和氧化物间隔物上方的凹陷中留下一层氧化物。然后使用化学机械抛光将氧化物抛光回氮化硅。该工艺提供优异的全局平面度，在不同尺寸和密度的有源区域上的氮化硅厚度的最小变化以及对芯片设计的相对不敏感性。

3. 发明授权

US5346584A Planarization process for IC trench isolation using oxidized polysilicon filler 失效
标题翻译：使用氧化多晶硅填料的IC沟槽隔离的平面化处理
公开(公告)号：US5346584A
公开(公告)日：1994-09-13
申请号：US98164
申请日：1993-07-28
申请人： Andre I. Nasr , Steven S. Cooperman
发明人： Andre I. Nasr , Steven S. Cooperman
IPC分类号： H01L21/763 , H01L21/306 , H01L21/304
CPC分类号： H01L21/763
摘要： Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.
摘要翻译：公开了在采用沟槽隔离技术的集成电路制造中对硅晶片的表面进行平面化的方法。半导体衬底上的沟槽和有源区域共形地涂覆有一层氧化硅。然后将一层图案化多晶硅沉积在氧化物的顶部上并被蚀刻以在沟槽上方的凹陷中产生填充块。接下来，将多晶硅退火，从而用膨胀的氧化物块填充沟槽。然后将所得的相对平坦的表面抛光回氮化物盖，从而在所有沟槽和有源区域尺寸上产生高度的平面度。

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