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1. 发明申请

US20120316855A1 Using Three-Dimensional Representations for Defect-Related Applications 审中-公开
标题翻译：使用三维表示缺陷相关应用程序
公开(公告)号：US20120316855A1
公开(公告)日：2012-12-13
申请号：US13156323
申请日：2011-06-08
申请人： Allen Park , Ellis Chang , Prashant A. Aji , Steven R. Lange
发明人： Allen Park , Ellis Chang , Prashant A. Aji , Steven R. Lange
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G01N21/9501 , G06F17/50 , G06F17/5009 , G06F2217/12 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments for using three-dimensional representations for defect-related applications are provided.
摘要翻译：提供了用于缺陷相关应用的三维表示的各种实施例。

2. 发明授权

US08923600B2 Methods and systems for utilizing design data in combination with inspection data 有权
标题翻译：利用设计数据结合检验数据的方法和系统
公开(公告)号：US08923600B2
公开(公告)日：2014-12-30
申请号：US12534547
申请日：2009-08-03
申请人： Khurram Zafar , Sagar Kekare , Ellis Chang , Allen Park , Peter Rose
发明人： Khurram Zafar , Sagar Kekare , Ellis Chang , Allen Park , Peter Rose
IPC分类号： G06K9/00 , G06F17/50 , G03F1/84
CPC分类号： G06T7/0006 , G03F1/84 , G06F17/5081 , G06T7/0008 , G06T2207/20076 , G06T2207/30148
摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.
摘要翻译：提供了与检测数据结合使用设计数据的各种方法和系统。用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。该方法还包括将合并步骤的结果存储在存储介质中。

3. 发明申请

US20110170091A1 INSPECTION GUIDED OVERLAY METROLOGY 有权
标题翻译：检查指导覆盖度量
公开(公告)号：US20110170091A1
公开(公告)日：2011-07-14
申请号：US12984679
申请日：2011-01-05
申请人： Ellis Chang , Amir Widmann , Allen Park
发明人： Ellis Chang , Amir Widmann , Allen Park
IPC分类号： G01N21/00
CPC分类号： G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.
摘要翻译：检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案，为半导体晶片上的预定图案的所有实例生成护理区域，通过执行检查扫描来检查所产生的护理区域内的缺陷每个生成的护理区域，其中检查扫描包括低阈值或高灵敏度检查扫描，识别具有大于使用缺陷检查技术的所选覆盖规格的测量的覆盖误差的半导体晶片的预定图案的覆盖位置将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较，以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置，以及生成计量取样基于确定的位置进行计划。

4. 发明申请

US20090297019A1 METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA 有权
标题翻译：与检验数据组合使用设计数据的方法和系统
公开(公告)号：US20090297019A1
公开(公告)日：2009-12-03
申请号：US12534547
申请日：2009-08-03
申请人： Khurram Zafar , Sagar Kekare , Ellis Chang , Allen Park , Peter Rose
发明人： Khurram Zafar , Sagar Kekare , Ellis Chang , Allen Park , Peter Rose
IPC分类号： G06K9/00
CPC分类号： G06T7/0006 , G03F1/84 , G06F17/5081 , G06T7/0008 , G06T2207/20076 , G06T2207/30148
摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.
摘要翻译：提供了与检测数据结合使用设计数据的各种方法和系统。用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。该方法还包括将合并步骤的结果存储在存储介质中。

5. 发明授权

US07570796B2 Methods and systems for utilizing design data in combination with inspection data 有权
标题翻译：利用设计数据结合检验数据的方法和系统
公开(公告)号：US07570796B2
公开(公告)日：2009-08-04
申请号：US11561659
申请日：2006-11-20
申请人： Khurram Zafar , Sagar Kekare , Ellis Chang , Allen Park , Peter Rose
发明人： Khurram Zafar , Sagar Kekare , Ellis Chang , Allen Park , Peter Rose
IPC分类号： G06K9/00
CPC分类号： G06T7/0006 , G03F1/84 , G06F17/5081 , G06T7/0008 , G06T2207/20076 , G06T2207/30148
摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.
摘要翻译：提供了与检测数据结合使用设计数据的各种方法和系统。用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。该方法还包括将合并步骤的结果存储在存储介质中。

6. 发明授权

US08559001B2 Inspection guided overlay metrology 有权
公开(公告)号：US08559001B2
公开(公告)日：2013-10-15
申请号：US12984679
申请日：2011-01-05
申请人： Ellis Chang , Amir Widmann , Allen Park
发明人： Ellis Chang , Amir Widmann , Allen Park
IPC分类号： G01N21/00 , G01R31/26
CPC分类号： G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

7. 发明授权

US08594823B2 Scanner performance comparison and matching using design and defect data 有权
标题翻译：使用设计和缺陷数据扫描仪性能比较和匹配
公开(公告)号：US08594823B2
公开(公告)日：2013-11-26
申请号：US12919757
申请日：2010-07-12
申请人： Allen Park , Ellis Chang , Masami Aoki , Chris Chih-Chien Young , Martin Plihal , Michael John Van Riet
发明人： Allen Park , Ellis Chang , Masami Aoki , Chris Chih-Chien Young , Martin Plihal , Michael John Van Riet
IPC分类号： G06F19/00 , H01L21/66
CPC分类号： H01L22/12 , G03F7/70516 , G03F7/70625 , G03F7/70641 , G03F7/7065
摘要： A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.
摘要翻译：描述使用设计和缺陷数据匹配多个扫描仪的系统和方法。使用金色工具处理金色晶圆。使用第二工具处理第二晶片。两种工具都提供对焦/曝光调制。可以比较两个晶片的关键结构的晶片级空间特征，以评估扫描仪的行为。关键结构可以通过在具有相似图案的金色晶片上合并缺陷来识别。在一个实施例中，签名必须在一定百分比内匹配，或者第二工具被表征为“不匹配”。可以以类似的方式比较网状物，其中分别使用金色掩模版和第二掩模版来处理金色和第二晶片。

8. 发明申请

US20130064442A1 Determining Design Coordinates for Wafer Defects 有权
标题翻译：确定晶圆缺陷的设计坐标
公开(公告)号：US20130064442A1
公开(公告)日：2013-03-14
申请号：US13601891
申请日：2012-08-31
申请人： Ellis Chang , Michael J. Van Riet , Allen Park , Khurram Zafar , Santosh Bhattacharyya
发明人： Ellis Chang , Michael J. Van Riet , Allen Park , Khurram Zafar , Santosh Bhattacharyya
IPC分类号： G06K9/62
CPC分类号： G06T7/001 , G06T7/74 , G06T2207/30148
摘要： Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.
摘要翻译：提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。一种方法包括对准晶片的设计以通过检查工具对晶片上的多个条带中检测到的缺陷来检查工具图像，基于对准的结果确定每个缺陷在设计坐标中的位置，分别确定缺陷基于检测到每个缺陷的条带（条纹校正因子），每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置，针对每个多个条带的位置偏移，以及通过对这些缺陷应用适当的条纹校正因子来确定检测工具在多个条中检测到的其他缺陷的设计坐标。

9. 发明授权

US07711514B2 Computer-implemented methods, carrier media, and systems for generating a metrology sampling plan 有权
标题翻译：计算机实现的方法，载体介质和用于生成计量抽样计划的系统
公开(公告)号：US07711514B2
公开(公告)日：2010-05-04
申请号：US11837208
申请日：2007-08-10
申请人： Allen Park , Ellis Chang
发明人： Allen Park , Ellis Chang
IPC分类号： G01M19/00 , G06F11/30
CPC分类号： G05B23/0221
摘要： Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.
摘要翻译：提供了各种计算机实现的方法，载体介质和用于生成计量抽样计划的系统。用于生成计量取样计划的一种计算机实现的方法包括从包含各个缺陷的缺陷群体的一个或多个属性识别具有一个或多个属性异常的一个或多个单个缺陷。缺陷的群体位于晶片上的预定图案中。该方法还包括基于识别步骤的结果生成计量取样计划，使得在测量期间采样一个或多个所识别的单个缺陷所在的晶片上的一个或多个区域。

10. 发明申请

US20090043527A1 COMPUTER-IMPLEMENTED METHODS, CARRIER MEDIA, AND SYSTEMS FOR GENERATING A METROLOGY SAMPLING PLAN 有权
标题翻译：计算机实现方法，载体介质和用于生成计量采样计划的系统
公开(公告)号：US20090043527A1
公开(公告)日：2009-02-12
申请号：US11837208
申请日：2007-08-10
申请人： Allen Park , Ellis Chang
发明人： Allen Park , Ellis Chang
IPC分类号： G06F19/00
CPC分类号： G05B23/0221
摘要： Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.
摘要翻译：提供了各种计算机实现的方法，载体介质和用于生成计量抽样计划的系统。用于生成计量取样计划的一种计算机实现的方法包括从包含各个缺陷的缺陷群体的一个或多个属性识别具有一个或多个属性异常的一个或多个单个缺陷。缺陷的群体位于晶片上的预定图案中。该方法还包括基于识别步骤的结果生成计量取样计划，使得在测量期间采样一个或多个所识别的单个缺陷所在的晶片上的一个或多个区域。

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