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    • 8. 发明申请
    • INSPECTION GUIDED OVERLAY METROLOGY
    • 检查指导覆盖度量
    • US20110170091A1
    • 2011-07-14
    • US12984679
    • 2011-01-05
    • Ellis ChangAmir WidmannAllen Park
    • Ellis ChangAmir WidmannAllen Park
    • G01N21/00
    • G01N21/9501G01N21/95607G01N2021/8822G03F7/70633G03F7/7065H01L22/12H01L2924/0002H01L2924/00
    • Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.
    • 检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案,为半导体晶片上的预定图案的所有实例生成护理区域,通过执行检查扫描来检查所产生的护理区域内的缺陷 每个生成的护理区域,其中检查扫描包括低阈值或高灵敏度检查扫描,识别具有大于使用缺陷检查技术的所选覆盖规格的测量的覆盖误差的半导体晶片的预定图案的覆盖位置 将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较,以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置,以及生成计量取样 基于确定的位置进行计划。