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    • 3. 发明授权
    • Apparatus and methods for analyzing defects on a sample
    • 用于分析样品缺陷的装置和方法
    • US07345753B2
    • 2008-03-18
    • US11069343
    • 2005-02-28
    • Kris BhaskarArdis LiangMichael J. Van Riet
    • Kris BhaskarArdis LiangMichael J. Van Riet
    • G01N21/00
    • G06T7/0004G06T2207/30148
    • Disclosed are methods and apparatus for facilitating procedures implemented on an analysis tool are provided herein. In one embodiment, an apparatus includes an analyzer module arranged for managing an analyzer tool and causing a high resolution image generated by the analyzer tool to be presented in a display. The apparatus also includes an inspector interface module arranged for simulating an inspector interface in the display. The inspector interface includes features that are available on a corresponding inspection tool, and the inspector interface is based at least in part on defect results from the inspection tool. In one embodiment, the analyzer module executes without knowledge of the inspector interface module and visa versa, and the apparatus includes a synchronization mechanism that knows about these two modules and also is capable of communicating with these two modules.
    • 本文提供了用于促进在分析工具上实现的过程的方法和装置。 在一个实施例中,一种装置包括分析器模块,该分析器模块被布置用于管理分析器工具,并使分析仪工具产生的高分辨率图像呈现在显示器中。 该装置还包括检查器接口模块,其布置成用于模拟显示器中的检查器接口。 检查员界面包括在相应的检查工具上可用的功能,检查器界面至少部分地基于检查工具的缺陷结果。 在一个实施例中,分析器模块在没有检查器接口模块的知识的情况下执行,反之亦然,并且该装置包括知道这两个模块并且还能够与这两个模块进行通信的同步机制。
    • 5. 发明授权
    • Determining design coordinates for wafer defects
    • 确定晶圆缺陷的设计坐标
    • US09087367B2
    • 2015-07-21
    • US13601891
    • 2012-08-31
    • Ellis ChangMichael J. Van RietAllen ParkKhurram ZafarSantosh Bhattacharyya
    • Ellis ChangMichael J. Van RietAllen ParkKhurram ZafarSantosh Bhattacharyya
    • G06K9/62G06T7/00
    • G06T7/001G06T7/74G06T2207/30148
    • Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.
    • 提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。 一种方法包括对准晶片的设计以通过检查工具对晶片上的多个条带中检测到的缺陷来检查工具图像,基于对准的结果确定每个缺陷在设计坐标中的位置,分别确定缺陷 基于检测到每个缺陷的条带(条纹校正因子),每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置,针对每个多个条带的位置偏移,以及 通过对这些缺陷应用适当的条纹校正因子来确定检测工具在多个条中检测到的其他缺陷的设计坐标。