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1. 发明授权

US06546529B1 Method for performing coupling analysis 失效
标题翻译：执行耦合分析的方法
公开(公告)号：US06546529B1
公开(公告)日：2003-04-08
申请号：US09677362
申请日：2000-10-02
申请人： Allan H. Dansky , Michael A. Bowen , Peter J. Camporese , Alina Deutsch , Howard H. Smith
发明人： Allan H. Dansky , Michael A. Bowen , Peter J. Camporese , Alina Deutsch , Howard H. Smith
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.
摘要翻译：耦合噪声电压的确定性评估是许多物理和电气参数的函数，如布线级别，宽度，间距，网络拓扑，drv阻抗和转换速率。该评估需要电气建模和后续电路仿真来评估这些参数的灵敏度。这些敏感性可以归类为可以通过提取的物理设计数据直接相关联的耦合准则。本发明公开了当耦合噪声电压计算通常需要的所有参数不可用时，在集成电路设计早期使用耦合指南表的技术的开发和实现。步骤包括：创建集成电路的扁平布线图，识别集成电路上的耦合线段，跟踪集成电路上的导线互连图案，导出耦合的线段的电参数，以及生成具有用于多个电参数的参数。耦合准则表中的参数应用于导出的电气参数，并生成报告，列出导出的电气参数不符合耦合指南表中的参数。

2. 发明授权

US06323050B1 Method for evaluating decoupling capacitor placement for VLSI chips 失效
标题翻译：评估VLSI芯片去耦电容放置的方法
公开(公告)号：US06323050B1
公开(公告)日：2001-11-27
申请号：US09677285
申请日：2000-10-02
申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
发明人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
IPC分类号： H01L2166
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
摘要翻译：公开了一种评估超大规模集成芯片（VLSI）的去耦电容放置的方法。该方法中包括对每个去耦电容器的使用情况，与器件的距离以及器件和去耦电容器的位置的分析。还解决了组件的方向和尺寸。

3. 发明授权

US06415428B1 Minimal length method for positioning unit pins in a hierarchically designed VLSI chip 失效
标题翻译：用于在分层设计的VLSI芯片中定位单元引脚的最小长度方法
公开(公告)号：US06415428B1
公开(公告)日：2002-07-02
申请号：US09422287
申请日：1999-10-21
申请人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
发明人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.
摘要翻译：一种用于在不改变单元布置的情况下，将次优定位单元引脚识别和定位在分层设计的VSLI芯片中的方法，包括：生成平坦数据文件，使用包括用于单元引脚和宏引脚的数据的平面数据文件生成第一引脚日志使用包括网的宏引脚的数据的平坦数据文件生成第二引脚对数，使用第一引脚对数确定最小净长度，并使用第二引脚对数确定最小净长度，计算第使用第一引脚对数确定的最小净长度和使用第二引脚对数确定的最小净长度，通过将计算出的差异与阈值进行比较来重新定位所识别的次优定位单元引脚，从而识别次优定位单元引脚。

4. 发明授权

US06374394B1 Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip 失效
标题翻译：识别不是最佳定位在分层设计的VLSI芯片中的单元引脚的方法
公开(公告)号：US06374394B1
公开(公告)日：2002-04-16
申请号：US09422290
申请日：1999-10-21
申请人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
发明人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value, that net is identified so that the unit pins can be reassigned by the unit designer or designers.
摘要翻译：一种用于识别最初在分层VLSI设计中分配的单元销位置的方法，如果被实现，将增加单元引脚作为一部分的网的净长度。为了识别单元引脚，当单元集成到顶级设计中时，由单元设计人员分配的单元销位置变为不良位置的选择，将创建具有单元的完成的VLSI设计的“平面”文件位于芯片上，包括由单元设计师分配的针位置。平面文件不仅包括顶层单元数据和单元到单元净数据，而且还包括每个单元设计的宏数据和宏网数据。平面设计数据文件用于生成两个引脚日志; 一个针脚日志包括每个网络的增量长度，包括与单元设计者分配的单位引脚（如果有的话）相关联的增量长度。另一个引脚日志是相同的，除了它不包括单位引脚和与单元引脚相关联的增量净长度。针对每个网络运行市售程序，例如最小生成树（MST）或Steiner最小树程序; 一次针对引脚日志列表中的网络，其中包括由单元的设计者分配的引脚，并且一次针对不包括分配的单元引脚的引脚日志列表中的网络。 MST（或类似程序）对带有和不带引脚分配的网络文件的兴趣的输出是一个文本文件，其中包含网络名称，每个带有和不带有单元引脚的网络引脚数，以及与/ 没有单位引脚分配。如果差异超过阈值，则识别该网络，使得单元引脚可由单元设计者或设计者重新分配。

5. 发明授权

US06618844B2 Method for evaluating decoupling capacitor placement for VLSI chips 失效
公开(公告)号：US06618844B2
公开(公告)日：2003-09-09
申请号：US09896270
申请日：2001-06-29
申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
发明人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

6. 发明授权

US06418401B1 Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
标题翻译：针对频率相关串扰模拟的三维互连结构建模的高效方法
公开(公告)号：US06418401B1
公开(公告)日：2002-07-09
申请号：US09248667
申请日：1999-02-11
申请人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
发明人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.
摘要翻译：一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

7. 发明授权

US06618843B2 Method for evaluating decoupling capacitor placement for VLSI chips 失效
公开(公告)号：US06618843B2
公开(公告)日：2003-09-09
申请号：US09896269
申请日：2001-06-29
申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
发明人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

8. 发明授权

US06460169B1 Routing program method for positioning unit pins in a hierarchically designed VLSI chip 失效
公开(公告)号：US06460169B1
公开(公告)日：2002-10-01
申请号：US09422040
申请日：1999-10-21
申请人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
发明人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value a router program is run in isolation against each net without unit pins. Pins are placed where the wiring route for the net crosses each unit boundary.

9. 发明授权

US07319946B2 Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：使用频率相关RLC提取和建模技术的片上信号完整性和噪声验证方法
公开(公告)号：US07319946B2
公开(公告)日：2008-01-15
申请号：US10274861
申请日：2002-10-21
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：新的频率相关RLC提取和片上完整性和噪声验证的建模采用：A）用于收集相邻信号和电源导体坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音增益R 12的频率相关RL电路的技术。

10. 发明授权

US07844435B2 Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：具有片上信号完整性和使用频率相关RLC提取和建模技术的噪声验证的集成电路芯片
公开(公告)号：US07844435B2
公开(公告)日：2010-11-30
申请号：US11942270
申请日：2007-11-19
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：集成电路芯片具有新的频率相关RLC提取和建模，提供片上完整性和噪声验证，提取和建模采用：A）用于收集相邻信号和电源导线坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音补音R12的频率相关RL电路的技术。

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