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1. 发明授权

US5144163A Dynamic BiCMOS logic gates 失效
标题翻译：动态BiCMOS逻辑门
公开(公告)号：US5144163A
公开(公告)日：1992-09-01
申请号：US631283
申请日：1990-02-20
申请人： Akira Matsuzawa , Shota Nakashima , Haruyasu Yamada
发明人： Akira Matsuzawa , Shota Nakashima , Haruyasu Yamada
IPC分类号： H03K19/0944 , H03K19/096
CPC分类号： H03K19/0963 , H03K19/09448
摘要： A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.
摘要翻译：动态逻辑门包括用于与时钟同步地预充电逻辑门的预充电装置; 部分逻辑门被布置成使得根据逻辑输入的逻辑状态，允许电流在其两个端子之间流动或被切断; 其发射极接地的双极晶体管，以及用于在预充电期间内放电存储在双极晶体管的基极中的电荷的放电装置。通过将部分逻辑门的导通电流提供给双极晶体管基极并使用双极晶体管的高速电流放大作用，逻辑门通过突然放电电路的负载能力来加速逻辑运算。

2. 发明授权

US5164728A A/D converter with complementary interpolating voltage dividers 失效
标题翻译：具有互补内插分压器的A / D转换器
公开(公告)号：US5164728A
公开(公告)日：1992-11-17
申请号：US711014
申请日：1991-06-06
申请人： Akira Matsuzawa , Haruyasu Yamada
发明人： Akira Matsuzawa , Haruyasu Yamada
IPC分类号： H03M1/06 , H03M1/20 , H03M1/36
CPC分类号： H03M1/205 , H03M1/0682 , H03M1/365
摘要： A parallel type analog to digital (A/D) converter in which an input signal and reference voltages are differentially amplified by differential converting circuits, interpolation resistors are inserted between the outputs and between the complementary outputs of the differential converting circuits, and a tap voltage between the interpolation resistors is A/D converted, so that the A/D converter can operate at a high accuracy and at a high speed.
摘要翻译：一种并行型模拟（A / D）转换器，其中输入信号和参考电压由差分转换电路差分放大，内插电阻插入在差分转换电路的输出和互补输出之间，并且分接电压在内插电阻之间进行A / D转换，使得A / D转换器能够以高精度高速运行。

3. 发明授权

US5321402A Analog-to-digital conversion method and device 失效
标题翻译：模数转换方式和装置
公开(公告)号：US5321402A
公开(公告)日：1994-06-14
申请号：US983255
申请日：1992-11-30
申请人： Akira Matsuzawa , Haruyasu Yamada
发明人： Akira Matsuzawa , Haruyasu Yamada
IPC分类号： H03M1/12 , H03M1/16 , H03M1/36 , H03M1/14 , H03M1/34 , H03M1/44
CPC分类号： H03M1/165 , H03M1/361 , Y10T307/461 , Y10T307/469
摘要： Analog-to-digital conversion method and device using triangular vertex solution are disclosed. The method includes the steps of defining a first and a second boundary value between which a quantity to be analog-to-digital converted resides, multiplying a difference between the first boundary value and the quantity to be converted by a first coefficient to produce a first physical quantity, multiplying a difference between the second boundary value and the quantity to be converted by a second coefficient to produce a second physical quantity, comparing the first and second physical quantities to obtain a comparison result, and logically converting the comparison result into a digital value. The device includes a first differential converting circuit for generating one or more voltages, which are produced by multiplying a potential difference between a first reference voltage and an input analog voltage by a chain of first coefficients, a second differential converting circuit for generating one or more voltages, which are produced by multiplying a potential difference between a second reference voltage and the input analog voltage by a chain of second coefficients, and a comparator circuit for comparing output voltages of the first and second differential converting circuits, with the output of the comparator circuit being logically converted into a digital value.
摘要翻译：公开了使用三角形顶点解的模数转换方法和装置。该方法包括以下步骤：定义第一和第二边界值，在该第一边界值和第二边界值之间存在要模数转换的数量，乘以第一边界值和要转换的数量之间的差值乘以第一系数，以产生第一物理量，将第二边界值和要转换的数量之间的差乘以第二系数以产生第二物理量，比较第一和第二物理量以获得比较结果，并将比较结果逻辑转换为数字值。该装置包括用于产生一个或多个电压的第一差分转换电路，其通过将第一参考电压和输入模拟电压之间的电位差乘以第一系数链而产生，第二差分转换电路，用于产生一个或多个通过将第二参考电压和输入模拟电压之间的电位差乘以第二系数链产生的电压以及用于比较第一和第二差分转换电路的输出电压与比较器的输出的比较器电路电路逻辑转换成数字值。

4. 发明授权

US5121002A Dynamic logic gates 失效
标题翻译：动态逻辑门
公开(公告)号：US5121002A
公开(公告)日：1992-06-09
申请号：US324038
申请日：1989-03-14
申请人： Akira Matsuzawa , Shota Nakashima , Haruyasu Yamada
发明人： Akira Matsuzawa , Shota Nakashima , Haruyasu Yamada
IPC分类号： H03K19/0944 , H03K19/096
CPC分类号： H03K19/09448 , H03K19/0963
摘要： A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.
摘要翻译：动态逻辑门包括用于与时钟同步地对逻辑门进行预充电的预充电装置; 部分逻辑门被布置成使得根据逻辑输入的逻辑状态，允许在其两个端子之间流动的电流或被切断; 发射极接地的双极晶体管，以及用于在预充电期间内放电存储在双极晶体管的基极中的电荷的放电装置。通过将部分逻辑门的导通电流提供给双极晶体管基极并使用双极型晶体管的高速电流放大作用，逻辑门通过突然放电电路的负载能力来加速逻辑运算。

5. 发明授权

US5034628A Fast trailing BIMOS logic gate 失效
标题翻译：快速拖尾BIMOS逻辑门
公开(公告)号：US5034628A
公开(公告)日：1991-07-23
申请号：US350250
申请日：1989-05-11
申请人： Akira Matsuzawa , Haruyasu Yamada
发明人： Akira Matsuzawa , Haruyasu Yamada
IPC分类号： H03K17/567 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448
摘要： The invention relates to a BIMOS logic gate comprising: a bipolar transistor; and depletion type MOS transistors whose sources are connected to a base of the bipolar transistor or MOS transistors having a threshold voltage smaller than that of MOS transistors constructing another complementary type logic circuit. A current of the bipolar transistor flows at an input voltage lower than that of the related art BIMOS logic gate and the current can be cut off by an input voltage which is equal to that of the ordinary complementary type logic circuit. Thus, the gate operates at a low electric power and can operate at a high speed at a low power source voltage.
摘要翻译：本发明涉及一种BIMOS逻辑门，包括：双极晶体管; 以及耗尽型MOS晶体管，其源极连接到双极晶体管的基极或具有小于构成另一互补型逻辑电路的MOS晶体管的阈值电压的MOS晶体管。双极晶体管的电流在比现有技术的BIMOS逻辑门低的输入电压下流动，并且可以通过等于普通互补型逻辑电路的输入电压来切断电流。因此，栅极以低功率运行，并且可以在低电源电压下以高速运行。

6. 发明授权

US5019820A Serial-parallel type A/D converter having reference resistor chain and current source array 失效
标题翻译：具有参考电阻链和电流源阵列的串并联型A / D转换器
公开(公告)号：US5019820A
公开(公告)日：1991-05-28
申请号：US400311
申请日：1989-08-29
申请人： Akira Matsuzawa , Haruyasu Yamada
发明人： Akira Matsuzawa , Haruyasu Yamada
IPC分类号： H03M1/14 , H03M1/06
CPC分类号： H03M1/069 , H03M1/147
摘要： A serial-parallel type a/d converter comprises first comparators whose one input is supplied with an input signal, for producing upper-digit signals; a circuit for supplying first different potentials determined according to arithmetic progression with respect to a reference potential to respective another input of the first comparators when the control signal is of first state, and for producing N-1 second different potentials with difference 1/N of voltage difference of first potentials over potential P (N, P: natural numbers) given by the upper-digit signals when the control signal is of second state; and N-1 second comparators whose one input is supplied with the input signal and another input is supplied with the respective second different potentials for producing lower-digit signals. A second a/d converter further comprises a circuit for additional reference potentials and additional comparators to make the lower-digit conversion range larger than one unit of the upper-digit conversion to improve conversion speed limited by settling time. Also, the upper-digit can be corrected by output from additional comparators. The number of comparators is reduced by switches for switching over from upper-digit to lower-digit potentials sent to the comparators.
摘要翻译：串行并行型a / d转换器包括第一比较器，其一个输入端被提供有输入信号，用于产生高位数字信号; 电路，用于当控制信号处于第一状态时，将相对于参考电位的算术进位确定的第一不同电位提供给第一比较器的另一输入，并且产生具有差值1 / N的N-1个第二不同电位当控制信号处于第二状态时，由高位数字信号给出的第一电势的电压差超过电位P（N，P：自然数）; 和一个输入端被提供有输入信号的N-1个第二比较器，另一个输入端被提供有用于产生低位数字信号的各自的第二不同电位。第二个a / d转换器还包括用于附加参考电位的电路和附加比较器，以使得低位数转换范围大于高位数转换的一个单位，以提高由建立时间限制的转换速度。此外，高位数可以通过附加比较器的输出进行校正。比较器的数量由发送到比较器的从高位数转换为低位数电位的开关减少。

7. 发明授权

US4963874A Parallel type A/D converter 失效
标题翻译：并行型A / D转换器
公开(公告)号：US4963874A
公开(公告)日：1990-10-16
申请号：US187642
申请日：1988-04-28
申请人： Akira Matsuzawa , Haruyasu Yamada
发明人： Akira Matsuzawa , Haruyasu Yamada
IPC分类号： H03M1/08 , H03M1/36
CPC分类号： H03M1/0809 , H03M1/365
摘要： A parallel type A/D converter includes circuitry for generating plural reference voltages, comparators for comparing the plural reference voltages with an input voltage, logic circuits for logically processing the outputs of comparators, and an encoder circuit for encoding the outputs from the logic circuits. A pair of logic outputs are obtained by a first logic circuit chain for receiving as inputs the outputs of a comparator of number i and of a comparator i+2. Conversion errors are reduced by properly processing this pair of logic outputs in a second logic circuit, or by composing an encoder circuit for receiving the pair of logic outputs as inputs.
摘要翻译：并行型A / D转换器包括用于产生多个参考电压的电路，用于将多个参考电压与输入电压进行比较的比较器，用于逻辑处理比较器的输出的逻辑电路和用于对来自逻辑电路的输出进行编码的编码器电路。一对逻辑输出由第一逻辑电路链获得，用于接收数字i和比较器i + 2的比较器的输出作为输入。通过在第二逻辑电路中适当地处理这对逻辑输出，或通过组合用于接收一对逻辑输出作为输入的编码器电路来减少转换误差。

8. 发明授权

US4459496A Semiconductor integrated circuit having stacked integrated injection logic circuits 失效
标题翻译：具有层叠集成注入逻辑电路的半导体集成电路
公开(公告)号：US4459496A
公开(公告)日：1984-07-10
申请号：US251966
申请日：1981-04-03
申请人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
发明人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
IPC分类号： H03K19/091 , H03K19/092
CPC分类号： H03K19/091
摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.
摘要翻译：在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。

9. 发明授权

US4791677A Image signal processor 失效
标题翻译：图像信号处理器
公开(公告)号：US4791677A
公开(公告)日：1988-12-13
申请号：US941625
申请日：1986-12-11
申请人： Toshiki Mori , Haruyasu Yamada , Kunitoshi Aono , Masakatsu Maruyama
发明人： Toshiki Mori , Haruyasu Yamada , Kunitoshi Aono , Masakatsu Maruyama
IPC分类号： G06T5/20 , G06K9/36 , G06F15/336 , G06K9/64
CPC分类号： G06T5/20
摘要： An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.
摘要翻译：一种图像信号处理器，包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m行x1列像素的扩展使用寄存器。因此，可以容易地进行局部图像区域的扩展和并行处理。

10. 发明授权

US5066602A Method of making semiconductor IC including polar transistors 失效
标题翻译：制造包含极性晶体管的半导体IC的方法
公开(公告)号：US5066602A
公开(公告)日：1991-11-19
申请号：US295380
申请日：1989-01-10
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092
CPC分类号： H01L27/0244 , H01L21/74 , H01L21/761 , H01L21/82285 , H01L27/0623 , H01L27/0826 , H01L27/0922 , Y10S148/009 , Y10S148/151
摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

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