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1. 发明授权

US5066602A Method of making semiconductor IC including polar transistors 失效
标题翻译：制造包含极性晶体管的半导体IC的方法
公开(公告)号：US5066602A
公开(公告)日：1991-11-19
申请号：US295380
申请日：1989-01-10
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092
CPC分类号： H01L27/0244 , H01L21/74 , H01L21/761 , H01L21/82285 , H01L27/0623 , H01L27/0826 , H01L27/0922 , Y10S148/009 , Y10S148/151
摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

2. 发明授权

US4845767A Image signal processor 失效
标题翻译：图像信号处理器
公开(公告)号：US4845767A
公开(公告)日：1989-07-04
申请号：US266893
申请日：1988-11-03
申请人： Toshiki Mori , Haruyasu Yamada , Kunitoshi Aono , Masakatsu Maruyama
发明人： Toshiki Mori , Haruyasu Yamada , Kunitoshi Aono , Masakatsu Maruyama
IPC分类号： G06T5/20
CPC分类号： G06T5/20
摘要： An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.1 column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.
摘要翻译：一种图像信号处理器，其包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m row×1列像素的扩展使用寄存器。因此，可以容易地进行局部图像区域的扩展和并行处理。

3. 发明授权

US4441198A Shift register circuit 失效
标题翻译：移位寄存器电路
公开(公告)号：US4441198A
公开(公告)日：1984-04-03
申请号：US275848
申请日：1981-06-22
申请人： Jun Shibata , Haruyasu Yamada , Toshiki Mori , Toyoki Takemoto
发明人： Jun Shibata , Haruyasu Yamada , Toshiki Mori , Toyoki Takemoto
IPC分类号： G11C19/00 , H03M1/00 , G11C19/28 , H03K19/173
CPC分类号： G11C19/00 , H03M1/38
摘要： A first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.
摘要翻译：第一逻辑电路包括耦合由不同相位的时钟脉冲驱动的门电路，经由耦合门电路级联的触发器电路和用于将触发器电路的输出反馈到前级触发电路的反馈电路并产生不同相位的脉冲序列。第二逻辑电路还包括由用于由第一逻辑电路产生的脉冲序列驱动的每个触发器电路的锁存电路。这些逻辑电路对逐次逼近A / D转换器的逐次逼近寄存器是有用的。

4. 发明授权

US5144163A Dynamic BiCMOS logic gates 失效
标题翻译：动态BiCMOS逻辑门
公开(公告)号：US5144163A
公开(公告)日：1992-09-01
申请号：US631283
申请日：1990-02-20
申请人： Akira Matsuzawa , Shota Nakashima , Haruyasu Yamada
发明人： Akira Matsuzawa , Shota Nakashima , Haruyasu Yamada
IPC分类号： H03K19/0944 , H03K19/096
CPC分类号： H03K19/0963 , H03K19/09448
摘要： A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.
摘要翻译：动态逻辑门包括用于与时钟同步地预充电逻辑门的预充电装置; 部分逻辑门被布置成使得根据逻辑输入的逻辑状态，允许电流在其两个端子之间流动或被切断; 其发射极接地的双极晶体管，以及用于在预充电期间内放电存储在双极晶体管的基极中的电荷的放电装置。通过将部分逻辑门的导通电流提供给双极晶体管基极并使用双极晶体管的高速电流放大作用，逻辑门通过突然放电电路的负载能力来加速逻辑运算。

5. 发明授权

US4791677A Image signal processor 失效
标题翻译：图像信号处理器
公开(公告)号：US4791677A
公开(公告)日：1988-12-13
申请号：US941625
申请日：1986-12-11
申请人： Toshiki Mori , Haruyasu Yamada , Kunitoshi Aono , Masakatsu Maruyama
发明人： Toshiki Mori , Haruyasu Yamada , Kunitoshi Aono , Masakatsu Maruyama
IPC分类号： G06T5/20 , G06K9/36 , G06F15/336 , G06K9/64
CPC分类号： G06T5/20
摘要： An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.
摘要翻译：一种图像信号处理器，包括用于接收m行×x列像素的本地图像区域数据的本地图像寄存器和耦合到本地图像寄存器的输出的m行x1列像素的扩展使用寄存器。因此，可以容易地进行局部图像区域的扩展和并行处理。

6. 发明授权

US4459496A Semiconductor integrated circuit having stacked integrated injection logic circuits 失效
标题翻译：具有层叠集成注入逻辑电路的半导体集成电路
公开(公告)号：US4459496A
公开(公告)日：1984-07-10
申请号：US251966
申请日：1981-04-03
申请人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
发明人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
IPC分类号： H03K19/091 , H03K19/092
CPC分类号： H03K19/091
摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.
摘要翻译：在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。

7. 发明授权

US5661066A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5661066A
公开(公告)日：1997-08-26
申请号：US965967
申请日：1991-04-02
申请人： Toyoki Takemoto , Haruyasu Yamada , Tsutomu Fujita , Tadao Komeda
发明人： Toyoki Takemoto , Haruyasu Yamada , Tsutomu Fujita , Tadao Komeda
IPC分类号： H01L21/8222 , H01L27/02 , H01L27/06 , H01L29/8605 , H01L29/93 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/0233 , H01L21/8222 , H01L27/0244 , H01L27/0647 , H01L29/8605 , H01L29/93
摘要： In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.
摘要翻译：在包括IIL和高频npn双极晶体管的集成电路中，其具有用于其反相npn输出晶体管的深p型基极区45，电路元件如电阻器部分R，电容器部分C，二极管部分D 并且隔离交叉连接部分Cr设置有与IIL中的p型区域45同时形成的深P型区域54,54'，65'，71和82，从而可靠性的电路元件及其特性得到改善，从而进一步提高了制造成品率。

8. 发明授权

US5164728A A/D converter with complementary interpolating voltage dividers 失效
标题翻译：具有互补内插分压器的A / D转换器
公开(公告)号：US5164728A
公开(公告)日：1992-11-17
申请号：US711014
申请日：1991-06-06
申请人： Akira Matsuzawa , Haruyasu Yamada
发明人： Akira Matsuzawa , Haruyasu Yamada
IPC分类号： H03M1/06 , H03M1/20 , H03M1/36
CPC分类号： H03M1/205 , H03M1/0682 , H03M1/365
摘要： A parallel type analog to digital (A/D) converter in which an input signal and reference voltages are differentially amplified by differential converting circuits, interpolation resistors are inserted between the outputs and between the complementary outputs of the differential converting circuits, and a tap voltage between the interpolation resistors is A/D converted, so that the A/D converter can operate at a high accuracy and at a high speed.
摘要翻译：一种并行型模拟（A / D）转换器，其中输入信号和参考电压由差分转换电路差分放大，内插电阻插入在差分转换电路的输出和互补输出之间，并且分接电压在内插电阻之间进行A / D转换，使得A / D转换器能够以高精度高速运行。

9. 发明授权

US4635292A Image processor 失效
标题翻译：图像处理器
公开(公告)号：US4635292A
公开(公告)日：1987-01-06
申请号：US682321
申请日：1984-12-17
申请人： Toshiki Mori , Haruyasu Yamada , Kenichi Hasegawa , Kunitoshi Aono
发明人： Toshiki Mori , Haruyasu Yamada , Kenichi Hasegawa , Kunitoshi Aono
IPC分类号： G06T5/20 , G06F9/28 , G06F15/66 , G06K9/36
CPC分类号： G06T5/20
摘要： This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.
摘要翻译：本发明提供并行部分图像处理，例如使用可以容易地形成为大规模集成电路并可用于各种目的的图像处理器的空间卷积或非线性相邻算术运算。图像处理器具有加法器 - 减法器，乘法器，互易数存储器，其中地址的倒数和移位量存储在每个地址处，以及移位寄存器。因此，处理器能够通过将乘数乘以乘法器的倒数并通过移位乘法结果来进行高速分频操作。此外，通过在程序控制下将输入切换到加法器 - 减法器和乘法器，可以对存储在部分图像存储器中的m行和n列的部分图像数据执行任意加法，减法，乘法和除法图像处理器。

10. 发明授权

US4233615A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4233615A
公开(公告)日：1980-11-11
申请号：US933045
申请日：1978-08-10
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Michihiro Inoue
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Michihiro Inoue
IPC分类号： H01L29/80 , H01L21/337 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/78 , H01L29/808
CPC分类号： H01L29/78 , H01L29/808
摘要： An IC device comprising a junction type field effect transistor of a back gate type and a bipolar device such as a bipolar transistor and a resistor made of impurity diffused region, wherein an extremely thin (in the order of 0.05-0.2 .mu.m) impurity doped surface region of a conductivity type same as that of a back gate region is formed at the surface of a surface channel region, and is separated from at least a drain region to sustain high breakdown voltage between gate region and the drain region; the impurity surface region serving to reduce noise and also enabling to achieve satisfactory characteristics of J-FET and also good ohmic characteristics of the resistor.
摘要翻译：一种IC器件，包括背栅型的结型场效应晶体管和双极晶体管的双极器件和由杂质扩散区域制成的电阻器，其中极薄（约0.05-0.2μm）的杂质掺杂在表面沟道区域的表面形成与背栅极区域相同的导电类型的表面区域，并且至少从漏极区域分离以维持栅极区域与漏极区域之间的高的击穿电压; 杂质表面区域用于降低噪声，并且还能够实现令人满意的J-FET特性和电阻器的良好欧姆特性。

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