专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07336116B2 Clock supply circuit 有权
标题翻译：时钟供电电路
公开(公告)号：US07336116B2
公开(公告)日：2008-02-26
申请号：US11342568
申请日：2006-01-31
申请人： Akio Hirata , Takahiro Ichinomiya , Takashi Ando
发明人： Akio Hirata , Takahiro Ichinomiya , Takashi Ando
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.
摘要翻译：本发明的时钟供给电路包括多个时钟供给路径和时钟门电路。时钟供应路径分支时钟信号，并且经由缓冲器将每个分支时钟信号提供给多个顺序电路。时钟门电路至少插入到时钟供给路径中的一个，当控制信号处于第一逻辑状态时，时钟供给路径通过时钟信号，并且当控制信号处于第二逻辑状态时，输出反相信号在施加第二逻辑状态的控制信号的前一时刻输出的逻辑电平。

2. 发明申请

US20060170479A1 Clock supply circuit 有权
标题翻译：时钟供电电路
公开(公告)号：US20060170479A1
公开(公告)日：2006-08-03
申请号：US11342568
申请日：2006-01-31
申请人： Akio Hirata , Takahiro Ichinomiya , Takashi Ando
发明人： Akio Hirata , Takahiro Ichinomiya , Takashi Ando
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.
摘要翻译：本发明的时钟供给电路包括多个时钟供给路径和时钟门电路。时钟供应路径分支时钟信号，并且经由缓冲器将每个分支时钟信号提供给多个顺序电路。时钟门电路至少插入到时钟供给路径中的一个，当控制信号处于第一逻辑状态时，时钟供给路径通过时钟信号，并且当控制信号处于第二逻辑状态时，输出反相信号在施加第二逻辑状态的控制信号的前一时刻输出的逻辑电平。

3. 发明申请

US20100100219A1 FABRICATION SYSTEM OF SEMICONDUCTOR INTEGRATED CIRCUIT, FABRICATION DEVICE, FABRICATION METHOD, INTEGRATED CIRCUIT AND COMMUNICATION SYSTEM 失效
标题翻译：半导体集成电路制造系统，制造装置，制造方法，集成电路和通信系统
公开(公告)号：US20100100219A1
公开(公告)日：2010-04-22
申请号：US12523834
申请日：2008-11-14
申请人： Takahiro Ichinomiya , Takashi Hashimoto
发明人： Takahiro Ichinomiya , Takashi Hashimoto
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , H01L27/118
摘要： A manufacturing system which can restrain the margin of a semiconductor integrated circuit.The integrated circuit 3000 including a fixed circuit unit 3003 and a reconfigurable circuit unit 3004 outputs, to a configuration determining server, an operation time which was calculated by a detecting unit 3001 and a calculating unit 3002. The configuration determining server 3007, by using the operation time obtained from the integrated circuit 3000, calculates performance data which indicates the characteristics of the fixed circuit unit 3003, selects, based on the performance data, a piece of configuration information indicating a circuit configuration that is optimum for the processing of the reconfigurable circuit unit 3004, and outputs the selected piece of configuration information.The integrated circuit 3000 builds a circuit in the reconfigurable circuit unit 3004 in accordance with the output piece of configuration information.
摘要翻译：能够抑制半导体集成电路的余量的制造系统。包括固定电路单元3003和可重构电路单元3004的集成电路3000将由检测单元3001和计算单元3002计算出的操作时间输出到配置确定服务器。配置确定服务器3007通过使用从集成电路3000获得的运算时间，计算表示固定电路单元3003的特性的性能数据，根据性能数据选择表示对于可重构电路的处理最佳的电路配置的一条配置信息单元3004，并输出所选择的配置信息。集成电路3000根据输出的配置信息构建可重构电路单元3004中的电路。

4. 发明授权

US07225418B2 Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same 有权
标题翻译：半导体集成电路器件的运行分析方法，使用的分析系统及其优化设计方法
公开(公告)号：US07225418B2
公开(公告)日：2007-05-29
申请号：US10863231
申请日：2004-06-09
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/31928
摘要： There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.
摘要翻译：包含通过基于电路信息计算电源端子处的半导体集成电路的每个实例的电压波形并分析各实例的电压波形来形成电压波形信息的步骤，通过以下步骤形成电压抽象信息：抽取电压波形信息，以及基于电压抽象信息计算实例的延迟值的步骤。

5. 发明授权

US08143913B2 Semiconductor integrated circuit, semiconductor integrated circuit control method, and terminal system 失效
标题翻译：半导体集成电路，半导体集成电路控制方法和终端系统
公开(公告)号：US08143913B2
公开(公告)日：2012-03-27
申请号：US12375853
申请日：2008-04-16
申请人： Takahiro Ichinomiya
发明人： Takahiro Ichinomiya
IPC分类号： H03K19/173
CPC分类号： H03K19/1774 , G06F1/10 , H03K5/1502 , H03K19/17784
摘要： A semiconductor integrated circuit judges whether a power unit is performing a discharge operation or a charge operation. To reduce clock skew between a plurality of logic blocks in the semiconductor integrated circuit, when the power unit is performing the charge operation, the semiconductor integrated circuit determines a logic block that needs to be operated for the execution of a target process, as an operation block whose operation is to be started, and, determines, in the rest of the logic blocks, a logic block having a termination rate whose value is larger than a value of the minimum termination rate, as the operation block whose operation is to be started, the value of the termination rate being larger by more than a predetermined value.
摘要翻译：半导体集成电路判断电力单元是进行放电动作还是充电动作。为了减少半导体集成电路中的多个逻辑块之间的时钟偏移，当功率单元正在进行充电操作时，半导体集成电路确定需要操作的逻辑块，以执行目标处理，作为操作块，其操作开始，并且在剩余的逻辑块中确定具有值大于最小终止速率值的终止速率的逻辑块作为其操作要开始的操作块，终止率的值大于预定值。

6. 发明授权

US07579864B2 Logic block control system and logic block control method 有权
标题翻译：逻辑块控制系统和逻辑块控制方法
公开(公告)号：US07579864B2
公开(公告)日：2009-08-25
申请号：US12093263
申请日：2006-11-15
申请人： Takahiro Ichinomiya
发明人： Takahiro Ichinomiya
IPC分类号： H03K19/173
CPC分类号： H03K19/1774 , H03K19/17784
摘要： The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the like is used.
摘要翻译：获得在可编程逻辑单元中执行目标处理时可以停止的块的数量，并且计算包括在可编程逻辑单元中的多个逻辑块中的每一个的停止率。以停止率的升序从多个逻辑块中选择与可停止的块相同数量的逻辑块，所选择的逻辑块被确定为其操作将被停止的逻辑块，并且操作是停了作为停止逻辑块的动作的技术，使用门控时钟技术，断电技术等。

7. 发明申请

US20050256921A1 Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method 审中-公开
标题翻译：延迟计算方法，时序分析法，计算对象网络近似法，延迟控制法等
公开(公告)号：US20050256921A1
公开(公告)日：2005-11-17
申请号：US10891496
申请日：2004-07-15
申请人： Naoki Amekawa , Takahiro Ichinomiya , Kazuhiro Satoh
发明人： Naoki Amekawa , Takahiro Ichinomiya , Kazuhiro Satoh
IPC分类号： G06F17/50 , G06G7/00 , H01L21/82 , H01L27/04 , H03K5/14
CPC分类号： G06F17/5036
摘要： A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.
摘要翻译：考虑与半导体集成电路的延迟计算对象网相邻的网络的延迟计算方法包括：相邻的网络内部电阻选择步骤，选择相邻网络驱动单元的静态的组合; 耦合电容接地步骤，将耦合电容乘以由相邻的净内部电阻选择步骤选择的相邻净驱动单元的内部电阻获得的系数等，并将由此获得的值接地作为延迟计算物体网; 以及延迟值导出步骤，从通过这些步骤获得的电路导出延迟值。通过这种结构解决了实际上电位波动近似为零电位的相邻导线的滞后计算方法不能获得精确延迟值的问题。

8. 发明申请

US20090327653A1 RECONFIGURABLE COMPUTING CIRCUIT 有权
标题翻译：可重构计算电路
公开(公告)号：US20090327653A1
公开(公告)日：2009-12-31
申请号：US12105551
申请日：2008-04-18
申请人： Masaki MAEDA , Takahiro Ichinomiya
发明人： Masaki MAEDA , Takahiro Ichinomiya
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/7867
摘要： A reconfigurable computing circuit for reducing amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block 2010, reg setting data selecting unit 3400 selects either a value stored in reg setting data storage unit 3000 or an initial value output from data reg data generating unit 4000, based on the information stored in reg type managing unit 1100 that indicates the types of registers and the connection order of the registers in the scan chain, and outputs the selected value in sequence to the scan chain under control of scan/reconfig control unit 1000. Each register in the scan chain then shifts data stored therein to the next register in the scan chain in sequence.
摘要翻译：一种可重构计算电路，用于减少存储在数据寄存器中的虚拟数据的数量，这是当配置信息总线和扫描链共享布线时所需要的。当数据被存储在重构计算块2010中构成扫描链的数据寄存器和配置寄存器中时，寄存器设置数据选择单元3400选择存储在寄存器设置数据存储单元3000中的值或从数据寄存器数据生成产生的初始值单元4000，基于存储在寄存器类型管理单元1100中的信息，其指示扫描链中的寄存器的类型和寄存器的连接顺序，并且在扫描/重新配置控制的控制下将所选择的值依次输出到扫描链单元1000.扫描链中的每个寄存器然后将存储在其中的数据顺序地移动到扫描链中的下一个寄存器。

9. 发明申请

US20050114054A1 Method for analyzing power supply noise of semiconductor integrated circuit 审中-公开
标题翻译：分析半导体集成电路电源噪声的方法
公开(公告)号：US20050114054A1
公开(公告)日：2005-05-26
申请号：US10988833
申请日：2004-11-16
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
IPC分类号： G06F17/50 , G01R29/26 , H01L21/82 , H01L21/822 , H01L27/04 , H03K17/16
CPC分类号： G01R29/26
摘要： Based on design data of a semiconductor integrated circuit, an impedance related to a power supply wire is calculated, and based on the calculated impedance, a frequency characteristic of power supply noise is analyzed. In calculation of an impedance, an impedance between power supplies which are different in potential, e.g., a main power supply and a ground, may be calculated. Alternatively, an impedance between power supplies which are substantially the same in potential, e.g., a main power supply and an N-well power supply, may be calculated. The calculated impedance includes a wire capacitance between power supply wires, a substrate resistance, an impedance of a package connected to the power supply wires, and so on. Thus, it is possible to provide a method for analyzing power supply noise of a semiconductor integrated circuit, which can be executed at an early stage of a design process with a small amount of calculation.
摘要翻译：基于半导体集成电路的设计数据，计算与电源线相关的阻抗，并且基于所计算的阻抗来分析电源噪声的频率特性。在计算阻抗时，可以计算电位不同的电源之间的阻抗，例如主电源和接地。或者，可以计算电位基本相同的电源之间的阻抗，例如主电源和N阱电源。所计算的阻抗包括电源线之间的线电容，衬底电阻，连接到电源线的封装的阻抗等。因此，可以提供一种用于分析半导体集成电路的电源噪声的方法，其可以在少量计算的设计过程的早期阶段执行。

10. 发明授权

US06440780B1 Method of layout for LSI 有权
标题翻译： LSI布局方法
公开(公告)号：US06440780B1
公开(公告)日：2002-08-27
申请号：US09613526
申请日：2000-07-10
申请人： Fumihiro Kimura , Takahiro Ichinomiya
发明人： Fumihiro Kimura , Takahiro Ichinomiya
IPC分类号： H01L2177
CPC分类号： G06F17/5068 , G06F17/505
摘要： The layout method of a semiconductor integrated circuit device according to the present invention includes a net list modification process for adding a cell to a flip-flop group directly connected to the clock source, a process for generating gated circuit division information which allocates the division number of the gated circuit and the drive ability of the cell so that the drive ability of the cell is selected and the delay value becomes uniform, a gated circuit division process for forming a cluster by dividing each of the gated circuits through clustering, a gated cell division process for allocating to each cluster the same number of gated cells as that of the formed clusters and a gated cell front stage CTS process in order to reduce the skew of the clock signal from the clock source via the gated cell to the flip-flop and to control the power consumption of the clock signal part.
摘要翻译：根据本发明的半导体集成电路器件的布局方法包括用于将单元添加到直接连接到时钟源的触发器组的净列表修改处理，用于生成分配电路划分信息的门控电路划分信息的处理门控电路的驱动能力和单元的驱动能力，使得选择单元的驱动能力并且延迟值变得均匀，用于通过聚类分割每个门控电路的门控电路划分过程，门控单元分配过程用于向每个群集分配与所形成的群集相同数量的门控单元，以及门控单元前级CTS处理，以便通过门控单元减少时钟信号从时钟源的偏移到触发器并控制时钟信号部分的功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式