专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150199198A1 SUPERVISOR MODE EXECUTION PROTECTION 有权
标题翻译：监督模式执行保护
公开(公告)号：US20150199198A1
公开(公告)日：2015-07-16
申请号：US13997857
申请日：2011-12-29
申请人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
发明人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30043 , G06F12/0292 , G06F12/1009 , G06F12/1491
摘要： Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.
摘要翻译：公开了用于监督模式执行保护的装置和方法。在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。存储器中的区域是用户存储器。执行硬件是执行指令。当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

2. 发明授权

US09323533B2 Supervisor mode execution protection 有权
标题翻译：主管模式执行保护
公开(公告)号：US09323533B2
公开(公告)日：2016-04-26
申请号：US13997857
申请日：2011-12-29
申请人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
发明人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
IPC分类号： G06F21/00 , H04L29/06 , G06F9/30 , G06F12/02 , G06F12/10 , G06F12/14 , G06F9/455 , G06F17/28
CPC分类号： G06F9/30189 , G06F9/30043 , G06F12/0292 , G06F12/1009 , G06F12/1491
摘要： Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.
摘要翻译：公开了用于监督模式执行保护的装置和方法。在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。存储器中的区域是用户存储器。执行硬件是执行指令。当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

3. 发明申请

US20120166767A1 SYSTEM, APPARATUS, AND METHOD FOR SEGMENT REGISTER READ AND WRITE REGARDLESS OF PRIVILEGE LEVEL 有权
标题翻译：系统，设备和分段注册读取和写入权限的优先权级别
公开(公告)号：US20120166767A1
公开(公告)日：2012-06-28
申请号：US12976981
申请日：2010-12-22
申请人： Baiju V. Patel , Gilbert Neiger , Martin G. Dixon , James S. Coke , James B. Crossland
发明人： Baiju V. Patel , Gilbert Neiger , Martin G. Dixon , James S. Coke , James B. Crossland
IPC分类号： G06F9/312
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/342
摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.
摘要翻译：描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。

4. 发明授权

US08938606B2 System, apparatus, and method for segment register read and write regardless of privilege level 有权
标题翻译：用于段寄存器读写的系统，设备和方法，无论权限级别如何
公开(公告)号：US08938606B2
公开(公告)日：2015-01-20
申请号：US12976981
申请日：2010-12-22
申请人： Baiju V. Patel , Gilbert Neiger , Martin G. Dixon , James S. Coke , James B. Crossland
发明人： Baiju V. Patel , Gilbert Neiger , Martin G. Dixon , James S. Coke , James B. Crossland
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/342
摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.
摘要翻译：描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。

5. 发明申请

US20110078389A1 MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS 有权
标题翻译：使用注册扩展管理和实施中央处理单元中的元数据
公开(公告)号：US20110078389A1
公开(公告)日：2011-03-31
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
IPC分类号： G06F9/30 , G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

6. 发明授权

US10515023B2 System for address mapping and translation protection 有权
公开(公告)号：US10515023B2
公开(公告)日：2019-12-24
申请号：US15088739
申请日：2016-04-01
申请人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
发明人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC分类号： G06F12/00 , G06F12/14 , G06F12/1009 , G06F9/455 , G06F12/1027 , G06F21/78
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

7. 发明授权

US08635415B2 Managing and implementing metadata in central processing unit using register extensions 有权
标题翻译：使用寄存器扩展管理和实施中央处理单元中的元数据
公开(公告)号：US08635415B2
公开(公告)日：2014-01-21
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jacob (Koby) Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jacob (Koby) Gottlieb
IPC分类号： G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

8. 发明授权

US09183391B2 Managing device driver cross ring accesses 有权
标题翻译：管理设备驱动程序交叉环路访问
公开(公告)号：US09183391B2
公开(公告)日：2015-11-10
申请号：US13997790
申请日：2013-03-13
申请人： Adriaan Van De Ven , Baiju V. Patel
发明人： Adriaan Van De Ven , Baiju V. Patel
IPC分类号： G06F11/00 , G06F12/14 , G06F12/16 , G08B23/00 , G06F21/56
CPC分类号： G06F21/56 , G06F12/1491 , G06F21/564 , G06F21/74 , G06F2212/1052 , G06F2221/2113
摘要： Technologies managing cross ring memory accesses by a device driver on a computing device includes configuring a memory page table associated with the device driver to disable cross ring memory accesses by the device driver, trapping attempted cross ring memory accesses by the device driver, and denying the attempted cross ring memory access if the device driver is determined to be malicious. If the device driver is determined not to be malicious, the memory page table is updated to allow the attempted cross ring memory access. The device driver may be analyzed to determine whether the device driver is malicious by comparing the device driver and the attempted cross ring memory access to security data, such as a device driver fingerprint and/or cross ring memory access heuristics, stored on the computing device.
摘要翻译：管理计算设备上的设备驱动器的交叉环存储器访问的技术包括配置与设备驱动程序相关联的存储器页表，以禁用设备驱动程序的交叉环存储器访问，捕获设备驱动程序尝试的交叉环存储器访问，以及拒绝如果设备驱动程序被确定为恶意，则尝试跨环内存访问。如果设备驱动程序被确定为不恶意，则更新内存页表以允许尝试的交叉环内存访问。可以分析设备驱动程序以通过将设备驱动程序和尝试的交叉环存储器访问与存储在计算设备上的安全数据（诸如设备驱动程序指纹和/或交叉环存储器访问启发式）进行比较来确定设备驱动程序是否是恶意的。

9. 发明申请

US20140115594A1 MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT OPERATING SYSTEM INTERVENTION 审中-公开
标题翻译：在没有操作系统干预的情况下安排在操作系统序列上的线程的机制
公开(公告)号：US20140115594A1
公开(公告)日：2014-04-24
申请号：US14067223
申请日：2013-10-30
申请人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
发明人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
IPC分类号： G06F9/48
CPC分类号： G06F9/4843
摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
摘要翻译：方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。调度程序例程可以在每个启用的顺控程序上运行。调度器可以从队列系统检索碎片描述符。与调度器相关联的定序器然后可以执行由描述符描述的碎片。还描述和要求保护其他实施例。

10. 发明授权

US08607235B2 Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention 有权
标题翻译：在没有操作系统干预的情况下安排操作系统隔离定序器上的线程的机制
公开(公告)号：US08607235B2
公开(公告)日：2013-12-10
申请号：US11027445
申请日：2004-12-30
申请人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
发明人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
摘要翻译：方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。调度程序例程可以在每个启用的顺控程序上运行。调度器可以从队列系统检索碎片描述符。与调度器相关联的定序器然后可以执行由描述符描述的碎片。还描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式