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1. 发明授权

US09006052B2 Self aligned device with enhanced stress and methods of manufacture 有权
标题翻译：具有增强应力和制造方法的自对准装置
公开(公告)号：US09006052B2
公开(公告)日：2015-04-14
申请号：US12901733
申请日：2010-10-11
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L21/00 , H01L29/786 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78654 , H01L29/66553 , H01L29/66651 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.
摘要翻译：一种方法包括在沉积在基底上的应力层中形成的沟槽中形成应力Si层。受应力的Si层形成器件的有源沟道区。该方法还包括在由应力Si层形成的有源沟道区中形成栅极结构。

2. 发明申请

US20120181578A1 PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION 审中-公开
标题翻译：前馈，源/排水应变层形成
公开(公告)号：US20120181578A1
公开(公告)日：2012-07-19
申请号：US13432018
申请日：2012-03-28
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/823412 , H01L29/66477 , H01L29/78 , H01L29/7842 , H01L29/7849
摘要： A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.
摘要翻译：一种方法产生晶体管。该方法在基层上形成应变产生层，然后去除应变产生层的至少一部分以在应变产生层中产生至少一个开口。这使得在基片上产生应变的层的第一和第二部分。应变产生层的第一和第二部分包括晶体管的源极和漏极应力区域。然后，该方法从基底层在应变产生层的开口中生长通道区域，在沟道区上形成栅极绝缘体，并在栅极绝缘体上形成栅极导体。

3. 发明申请

US20120104507A1 METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
标题翻译：在门电路第一流程中生长应变诱导材料的方法
公开(公告)号：US20120104507A1
公开(公告)日：2012-05-03
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

4. 发明申请

US20110215376A1 PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION 审中-公开
标题翻译：前馈，源/排水应变层形成
公开(公告)号：US20110215376A1
公开(公告)日：2011-09-08
申请号：US12719312
申请日：2010-03-08
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823412 , H01L29/66477 , H01L29/78 , H01L29/7842 , H01L29/7849
摘要： A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.
摘要翻译：一种方法产生晶体管。该方法在基层上形成应变产生层，然后去除应变产生层的至少一部分以在应变产生层中产生至少一个开口。这使得在基片上产生应变的层的第一和第二部分。应变产生层的第一和第二部分包括晶体管的源极和漏极应力区域。然后，该方法从基底层在应变产生层的开口中生长通道区域，在沟道区上形成栅极绝缘体，并在栅极绝缘体上形成栅极导体。

5. 发明授权

US09293593B2 Self aligned device with enhanced stress and methods of manufacture 有权
公开(公告)号：US09293593B2
公开(公告)日：2016-03-22
申请号：US13474257
申请日：2012-05-17
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L21/02 , H01L29/786 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78654 , H01L29/66553 , H01L29/66651 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.

6. 发明申请

US20120112208A1 STRESSED TRANSISTOR WITH IMPROVED METASTABILITY 有权
标题翻译：具有改进的均匀性的应力晶体管
公开(公告)号：US20120112208A1
公开(公告)日：2012-05-10
申请号：US12942289
申请日：2010-11-09
申请人： THOMAS N. ADAM , Stephen W. Bedell , Abhishek Dube , Eric C.T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
发明人： THOMAS N. ADAM , Stephen W. Bedell , Abhishek Dube , Eric C.T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L29/772 , H01L29/24 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76805 , H01L21/76877 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
摘要翻译：在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

7. 发明申请

US20120086046A1 SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE 有权
标题翻译：具有增强应力的自对准装置和制造方法
公开(公告)号：US20120086046A1
公开(公告)日：2012-04-12
申请号：US12901733
申请日：2010-10-11
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78654 , H01L29/66553 , H01L29/66651 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.
摘要翻译：一种方法包括在沉积在基底上的应力层中形成的沟槽中形成应力Si层。受应力的Si层形成器件的有源沟道区。该方法还包括在由应力Si层形成的有源沟道区中形成栅极结构。

8. 发明授权

US08492234B2 Field effect transistor device 有权
公开(公告)号：US08492234B2
公开(公告)日：2013-07-23
申请号：US12825791
申请日：2010-06-29
申请人： Kevin K. Chan , Abhishek Dube , Eric C. Harley , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman , Linda R. Black
发明人： Kevin K. Chan , Abhishek Dube , Eric C. Harley , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman , Linda R. Black
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L21/823412 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78618 , H01L29/78684
摘要： A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

9. 发明授权

US08361859B2 Stressed transistor with improved metastability 有权
标题翻译：具有改善的亚稳态的强调晶体管
公开(公告)号：US08361859B2
公开(公告)日：2013-01-29
申请号：US12942289
申请日：2010-11-09
申请人： Thomas N. Adam , Stephen W. Bedell , Abhishek Dube , Eric C. T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
发明人： Thomas N. Adam , Stephen W. Bedell , Abhishek Dube , Eric C. T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76805 , H01L21/76877 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
摘要翻译：在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

10. 发明授权

US08426265B2 Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
标题翻译：在栅极第一流中在CMOS电路中增长应变诱导材料的方法
公开(公告)号：US08426265B2
公开(公告)日：2013-04-23
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

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