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    • 6. 发明申请
    • METHOD AND APPARATUS FOR CONTROLLING PLASMA UNIFORMITY
    • 用于控制等离子体均匀性的方法和装置
    • WO2009082763A2
    • 2009-07-02
    • PCT/US2008088351
    • 2008-12-24
    • APPLIED MATERIALS INCKUDELA JOZEFFURUTA GAKUSORENSEN CARL ACHOI SOO YOUNGWHITE JOHN M
    • KUDELA JOZEFFURUTA GAKUSORENSEN CARL ACHOI SOO YOUNGWHITE JOHN M
    • H01L21/205H05H1/34
    • H01J37/32623C23C16/345C23C16/5096H01J37/32082
    • Systems, methods, and apparatus involve a plasma processing chamber (200, 200', 200'') for depositing a film (231) on a substrate (232). The plasma processing chamber (200) includes a lid assembly (214) having a ground plate (225), a backing plate (240), and a non-uniformity (201) existing between the ground plate (225) and the backing plate (240). The non-uniformity (201) may interfere with RF wave uniformity and cause an impedance imbalance between portions of the ground plate (225) and backing plate (240). The non-uniformity (201) may include a structure (300) or a reduced spacing (400) of non-uniform surfaces. A reduced spacing (400) of non-uniform surfaces may exist where a first distance (d1, d2) between the ground plate (225) and the backing plate (240) at a first end (402) is different from a second distance (d3) between the ground plate (225) and the backing plate (240) at a second end (404). The structure (300) may be from 2cm to 10cm thick, cover from 20% to 50% of the backing plate (240), and be located away from a discontinuity (207) existing inside the chamber (200').
    • 系统,方法和装置包括用于在衬底(232)上沉积膜(231)的等离子体处理室(200,200',200“)。 等离子体处理室(200)包括具有接地板(225),背板(240)和存在于接地板(225)和背板(2)之间的不均匀性(201)的盖组件 240)。 不均匀性(201)可能会干扰RF波均匀性,并导致接地板(225)和背板(240)的部分之间的阻抗不平衡。 不均匀性(201)可以包括不均匀表面的结构(300)或减小的间隔(400)。 可以存在不均匀表面的减小的间隔(400),其中在第一端(402)处的接地板(225)和背板(240)之间的第一距离(d1,d2)不同于第二距离 d3)在第二端(404)处于接地板(225)和背板(240)之间。 结构(300)可以为2cm至10cm厚,覆盖背板(240)的20%至50%,并且位于远离存在于室(200')内部的不连续(207)的位置。
    • 8. 发明申请
    • THIN FILM TRANSISTORS HAVING MULTIPLE DOPED SILICON LAYERS
    • 具有多层掺杂硅层的薄膜晶体管
    • WO2011056710A3
    • 2011-08-18
    • PCT/US2010054505
    • 2010-10-28
    • APPLIED MATERIALS INCFURUTA GAKUCHOI SOO YOUNGOMORI KENJI
    • FURUTA GAKUCHOI SOO YOUNGOMORI KENJI
    • H01L29/786G02F1/136
    • H01L29/66765G02F1/1362H01L29/78618
    • Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
    • 本发明的实施例一般涉及TFT及其制造方法。 本文公开的TFT是其中有源沟道包括非晶硅的硅基TFT。 在非晶硅上,沉积了多层掺杂的硅,其中掺杂硅层的电阻率在与非晶硅层的界面处比与源极和漏极的界面相比更高。 或者,在非晶硅上沉积单个掺杂的硅层,其中单个掺杂层的性质在整个厚度上变化。 在与源极和漏极的界面处具有较低的电阻率是更好的,但较低的电阻率通常意味着较少的衬底生产量。 通过利用多层或分层,可以实现低电阻率。 本文公开的实施例包括低电阻率而不牺牲基板生产量。