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1. 发明申请

WO2008121327A1 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：形成半导体结构的方法
公开(公告)号：WO2008121327A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/004066
申请日：2008-03-28
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , STEPHAN, Rolf , HORSTMANN, Manfred
发明人： WIRBELEIT, Frank , STEPHAN, Rolf , HORSTMANN, Manfred
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L21/28123 , H01L29/66545 , H01L29/6659
摘要： A method of forming a semiconductor structure (300) comprises providing a semiconductor substrate (201). A feature (306) is formed over the substrate (201). The feature (306) is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion (212, 213) of the substrate (201) adjacent the feature (306) is performed. The length (330) of the feature (306) in the lateral direction is reduced. After the reduction of the length (330) of the feature (306), a second ion implantation process adapted to introduce second dopant ions into at least one portion (209, 210) of the substrate (201) adjacent the feature (306) is performed. The feature (306) may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate (201).
摘要翻译：形成半导体结构（300）的方法包括提供半导体衬底（201）。在衬底（201）上形成特征（306）。特征（306）在横向上基本上是均匀的。执行适于将第一掺杂剂离子引入邻近特征（306）的衬底（201）的至少一个部分（212,213）中的第一离子注入工艺。特征（306）在横向上的长度（330）减小。在特征（306）的长度（330）减小之后，适于将第二掺杂离子引入邻近特征（306）的衬底（201）的至少一部分（209,210）中的第二离子注入工艺是执行。特征（306）可以是形成在半导体衬底（201）上的场效应晶体管的栅电极。

2. 发明申请

WO2008042144A2 A SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN 审中-公开
标题翻译：包含不同类型菌株的分离条件的半导体器件
公开(公告)号：WO2008042144A2
公开(公告)日：2008-04-10
申请号：PCT/US2007/020598
申请日：2007-09-24
申请人： ADVANCED MICRO DEVICES, INC. , SCHWAN, Christoph , BLOOMQUIST, Joe , JAVORKA, Peter , HORSTMANN, Manfred , BEYER, Sven , FORSBERG, Markus , WIRBELEIT, Frank , ROMERO, Karla
发明人： SCHWAN, Christoph , BLOOMQUIST, Joe , JAVORKA, Peter , HORSTMANN, Manfred , BEYER, Sven , FORSBERG, Markus , WIRBELEIT, Frank , ROMERO, Karla
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： By forming isolation trenches (102 A, 102B) of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions (105A, 105B) may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material (107A, 107B) including compressive and tensile stress may be appropriately provided in the respective isolation trenches (102A, 102B) in order to correspondingly adapt the charge carrier mobility of respective channel regions (121 A, 121B).
摘要翻译：通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽（102A，102B），可以调节相邻的有源半导体区域（105A，105B）的应变特性以获得整体器件性能。例如，可以在相应的隔离沟槽（102A，102B）中适当地提供包括压应力和拉伸应力的高应力电介质填充材料（107A，107B），以便相应地适应相应通道区域（121A，121B）的载流子迁移率）。

3. 发明申请

WO2006022946A1 TECHNIQUE FOR EVALUATING LOCAL ELECTRICAL CHARACTERISTICS IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于评估半导体器件中的局部电气特性的技术
公开(公告)号：WO2006022946A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/018357
申请日：2005-05-25
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BURBACH, Gert , WIECZOREK, Karsten , HORSTMANN, Manfred
发明人： WIRBELEIT, Frank , BURBACH, Gert , WIECZOREK, Karsten , HORSTMANN, Manfred
IPC分类号： H01L23/544
CPC分类号： H01L22/34
摘要： By providing a test structure (100) including a plurality of test pads (104), the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads (104) may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.
摘要翻译：通过提供包括多个测试焊盘（104）的测试结构（100），可以以高效的方式确定应力和应变影响的电特性（例如电子迁移率）的各向异性行为。此外，测试焊盘（104）可以以单个电路元件的数量级的空间分辨率来检测应力和应变诱发的修改。

4. 发明申请

WO2006022915A1 SELF-BIASING TRANSISTOR STRUCTURE AND SRAM CELL 审中-公开
标题翻译：自偏转晶体管结构和SRAM单元
公开(公告)号：WO2006022915A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/015294
申请日：2005-04-29
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , HORSTMANN, Manfred , HOBERT, Christian
发明人： WIRBELEIT, Frank , HORSTMANN, Manfred , HOBERT, Christian
IPC分类号： H01L29/78
CPC分类号： G11C11/412 , H01L27/11
摘要： By providing a self-biasing semiconductor switch, an SRAM cell (450) having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor (400) that allows the formation of an SRAM cell (450) with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.
摘要翻译：通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元（450）。在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管（400）的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元（450），并且在优选实施例中，只有两个单独的晶体管元件。

5. 发明申请

WO2010022974A1 BODY CONTACT FOR SRAM CELL COMPRISING DOUBLE-CHANNEL TRANSISTORS 审中-公开
标题翻译：身体接触用于包含双通道晶体管的SRAM单元
公开(公告)号：WO2010022974A1
公开(公告)日：2010-03-04
申请号：PCT/EP2009/006263
申请日：2009-08-28
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank
发明人： WIRBELEIT, Frank
IPC分类号： H01L21/8244 , H01L27/11 , G11C11/412 , H01L21/768 , H01L29/10 , H01L29/78 , H01L29/06
CPC分类号： H01L27/11 , H01L21/76895 , H01L27/1104 , H01L29/0623 , H01L29/105 , H01L29/7833
摘要： A static RAM cell (250) may be formed on the basis of two double channel transistors (200N, 200P) and a select transistor (200S), wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure (205A), while a further rectangular contact (230) may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may significantly be increased.
摘要翻译：可以基于两个双沟道晶体管（200N，200P）和选择晶体管（200S）形成静态RAM单元（250），其中主体接触可以侧向位于两个双通道晶体管之间，形式为伪栅极电极结构（205A），而另一个矩形触点（230）可以连接栅电极，源极区和体接触，从而建立到晶体管的体区的导电路径。因此，与常规身体接触相比，可以建立非常空间有效的配置，使得静态RAM单元中的位密度可以显着增加。

6. 发明申请

WO2008016505A1 METHOD FOR FORMING A STRAINED TRANSISTOR BY STRESS MEMORIZATION BASED ON A STRESSED IMPLANTATION MASK 审中-公开
标题翻译：基于压应力掩蔽的应力记忆形成应变晶体的方法
公开(公告)号：WO2008016505A1
公开(公告)日：2008-02-07
申请号：PCT/US2007/016579
申请日：2007-07-24
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BOSCHKE, Roman , GERHARDT, Martin
发明人： WIRBELEIT, Frank , BOSCHKE, Roman , GERHARDT, Martin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/7843 , H01L29/7848
摘要： By using an implantation mask having a high intrinsic stress, stress memorization technique (SMT) sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.
摘要翻译：通过使用具有高固有应力的注入掩模，可以提供应力存储技术（SMT）序列，其中可以避免额外的光刻步骤。因此，可以提供应变源而不显着地有助于整个工艺的复杂性。

7. 发明申请

WO2007037847A1 METHODS FOR FABRICATION OF A STRESSED MOS DEVICE 审中-公开
标题翻译：用于制造应力MOS器件的方法
公开(公告)号：WO2007037847A1
公开(公告)日：2007-04-05
申请号：PCT/US2006/032755
申请日：2006-08-23
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BLACK, Linda, R. , PEIDOUS, Igor
发明人： WIRBELEIT, Frank , BLACK, Linda, R. , PEIDOUS, Igor
IPC分类号： H01L21/336 , H01L29/06 , H01L21/8238 , H01L29/786 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/1037 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： Methods for fabricating a stressed MOS device [30] is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate [36] having a surface [32] and a channel [70] abutting the surface. A gate electrode [66] having a first edge [75] and a second edge [85] is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess [82] aligned with the first edge [75] and a second recess [84] aligned with the second edge [85]. The substrate is further isotropically etched to form a third recess [96] in the substrate extending beneath the channel [70]. The third recess is filled with an expanding material [100] to exert an upward force [101] on the channel and the first [82] and second [84] recesses are filled with a contact material [HO]. Conductivity determining ions are implanted into the contact material [110] to form a source region [130] and a drain region [132] aligned with the first [75] and second edges [85], respectively.
摘要翻译：提供了制造应力MOS器件的方法[30]。一种方法包括提供具有邻接表面的表面[32]和通道（70）的单晶半导体衬底[36]的步骤。具有第一边缘[75]和第二边缘（85）的栅极电极（66）形成在单晶半导体衬底上。衬底被各向异性地蚀刻以形成与第一边缘[75]对准的第一凹槽[82]和与第二边缘[85]对准的第二凹部[84]。衬底被进一步各向同性蚀刻，以在衬底下延伸到通道[70]下面的第三凹槽[96]。填充第三凹槽，以膨胀材料[100]向通道上施加向上的力[101]，并且第一凹槽（82）和第二凹槽（84）用接触材料[HO]填充。电导率确定离子被注入到接触材料[110]中以分别形成与第一边[75]和第二边[85]对准的源极区[130]和漏区[132]。

8. 发明申请

WO2009099557A1 A BODY CONTROLLED DOUBLE CHANNEL TRANSISTOR AND CIRCUITS COMPRISING THE SAME 审中-公开
标题翻译：一个身体控制的双通道晶体管和包含它的电路
公开(公告)号：WO2009099557A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/000602
申请日：2009-01-30
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank
发明人： WIRBELEIT, Frank
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L29/7841
摘要： By providing a body controlled double channel transistor (200, 400, 500P, 500N), increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits (550) usable for static RAM cells (560) may be formed on the basis of the body controlled double channel transistor (200, 400, 500P, 500N), thereby reducing the number of transistors required per cell, which may result in increased information density.
摘要翻译：通过提供体控双通道晶体管（200,400,500P，500N），可以实现与增强的稳定性相结合的增加的功能。例如，可以基于体控双通道晶体管（200,400,500P，500N）形成可用于静态RAM单元（560）的触发器电路（550），从而减少每个单元所需的晶体管数量，这可能导致信息密度增加。

9. 发明申请

WO2008016512A1 A TRANSISTOR HAVING A STRAINED CHANNEL REGION INCLUDING A PERFORMANCE ENHANCING MATERIAL COMPOSITION 审中-公开
标题翻译：具有应变通道区域的晶体管，包括性能增强材料组成
公开(公告)号：WO2008016512A1
公开(公告)日：2008-02-07
申请号：PCT/US2007/016612
申请日：2007-07-24
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , WEI, Andy , BOSCHKE, Roman
发明人： WIRBELEIT, Frank , WEI, Andy , BOSCHKE, Roman
IPC分类号： H01L29/10
CPC分类号： H01L29/66636 , H01L21/02238 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/31662 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/105 , H01L29/665 , H01L29/66651 , H01L29/7848
摘要： By forming a semiconductor alloy (107, 107A, 107B, 207A, 207B, 307) in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.
摘要翻译：通过在栅极图案化之前在硅基有源半导体区域中形成半导体合金（107,107A，107B，207A，207B，307），除了应变诱导之外，还可以利用半导体合金本身的材料特性效果。因此，与在漏极和源极区域中使用应变半导体合金的常规方法相比，先进的场效应晶体管的器件性能可以进一步提高。

10. 发明申请

WO2006130375A2 TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING AVERTICAL DOPANT PROFILE 审中-公开
标题翻译：通过适应平均眩晕配置文件减少硅酸盐非均质的技术
公开(公告)号：WO2006130375A2
公开(公告)日：2006-12-07
申请号：PCT/US2006/019722
申请日：2006-05-23
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BROWN, David , PRESS, Patrick
发明人： WIRBELEIT, Frank , BROWN, David , PRESS, Patrick
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By modifying the vertical dopant concentration in deep drain and source regions, the reaction behavior during the formation of metal suicide regions 217 may be controlled. For this purpose, an increased dopant concentration is formed around a target depth (X s ) for the metal suicide interface, thereby reducing the reaction speeds and thus improving the uniformity of the resulting metal suicide interface.
摘要翻译：通过改变深漏和源区中的垂直掺杂剂浓度，可以控制在形成金属硅化物区217期间的反应行为。为此，在金属硅化物界面的目标深度（X S）附近形成增加的掺杂剂浓度，从而降低反应速度，从而提高所得到的金属硅化物界面的均匀性。

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