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1. 发明申请

WO2006130375A2 TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING AVERTICAL DOPANT PROFILE 审中-公开
标题翻译：通过适应平均眩晕配置文件减少硅酸盐非均质的技术
公开(公告)号：WO2006130375A2
公开(公告)日：2006-12-07
申请号：PCT/US2006/019722
申请日：2006-05-23
申请人： ADVANCED MICRO DEVICES, INC. , WIRBELEIT, Frank , BROWN, David , PRESS, Patrick
发明人： WIRBELEIT, Frank , BROWN, David , PRESS, Patrick
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By modifying the vertical dopant concentration in deep drain and source regions, the reaction behavior during the formation of metal suicide regions 217 may be controlled. For this purpose, an increased dopant concentration is formed around a target depth (X s ) for the metal suicide interface, thereby reducing the reaction speeds and thus improving the uniformity of the resulting metal suicide interface.
摘要翻译：通过改变深漏和源区中的垂直掺杂剂浓度，可以控制在形成金属硅化物区217期间的反应行为。为此，在金属硅化物界面的目标深度（X S）附近形成增加的掺杂剂浓度，从而降低反应速度，从而提高所得到的金属硅化物界面的均匀性。

2. 发明申请

WO2008027473A2 A TRANSISTOR HAVING A LOCALLY PROVIDED METAL SILICIDE REGION IN CONTACT AREAS AND A METHOD OF FORMING THE TRANSISTOR 审中-公开
标题翻译：一种在接触区域内具有本地提供的金属硅化物区域的晶体管及一种形成晶体管的方法
公开(公告)号：WO2008027473A2
公开(公告)日：2008-03-06
申请号：PCT/US2007/019073
申请日：2007-08-29
申请人： ADVANCED MICRO DEVICES, INC. , BEYER, Sven , PRESS, Patrick , FEUDEL, Thomas
发明人： BEYER, Sven , PRESS, Patrick , FEUDEL, Thomas
IPC分类号： H01L21/768 , H01L21/285 , H01L21/336
CPC分类号： H01L21/823418 , H01L21/28052 , H01L21/28518 , H01L21/76877 , H01L21/76883 , H01L21/823412 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823871 , H01L29/41725 , H01L29/665 , H01L29/66507 , H01L29/7842 , H01L29/7845 , H01L29/7848
摘要： By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.
摘要翻译：通过基于图案化的电介质层（诸如层间电介质材料）执行硅化工艺，各个金属硅化物部分可以以高度局部化的方式设置在各个接触区域处，而金属硅化物的总量可能显着减少。以这种方式，金属硅化物对场效应晶体管的沟道区域的应力的负面影响可以显着减小，同时仍然保持低接触电阻。

3. 发明申请

WO2008054678A1 A SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 审中-公开
标题翻译：包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件
公开(公告)号：WO2008054678A1
公开(公告)日：2008-05-08
申请号：PCT/US2007/022680
申请日：2007-10-26
申请人： ADVANCED MICRO DEVICES INC. , BEYER, Sven , HORSTMANN, Manfred , PRESS, Patrick , BUCHHOLTZ, Wolfgang
发明人： BEYER, Sven , HORSTMANN, Manfred , PRESS, Patrick , BUCHHOLTZ, Wolfgang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： By forming a substantially continuous and uniform semiconductor alloy (107, 207, 307, 407) in one active region (105 A, 205 A, 305 A, 405 A) while patterning the semiconductor alloy (107, 207, 307, 407) in a second active region (105B, 205B, 3O5B, 405B) so as to provide a base semiconductor material (113B, 213B, 313B, 401) in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material (113A, 213A, 313A, 413A), well-established process techniques for forming the gate dielectric (122, 322, 422) may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode (121, 221, 321, 421) may be formed on the basis of the layer (208, 308), which has also been used for defining the central portion (213B, 313B) of the base semiconductor material of one of the active regions (205B, 305B). Hence, by using a single semiconductor alloy (107, 207, 307, 407), the performance of transistors (120A, 120B) of different conductivity types may be individually enhanced.
摘要翻译：通过在将半导体合金（107,207,307,407）图案化的同时在一个有源区（105A，205A，305A，405A）中形成基本上连续且均匀的半导体合金（107,207,307,407）第二有源区域（105B，205B，30B，405B），以便在其中心部分提供基极半导体材料（113B，213B，313B，401），可以诱发不同类型的应变，而在提供相应的基底半导体材料（113A，213A，313A，413A）的覆盖层可以使用用于形成栅极电介质（122,322,422）的完善的工艺技术。在一些说明性实施例中，提供基本上自对准的工艺，其中可以基于层（208,308）形成栅电极（121,221,321,421），其也已经用于限定一个有源区域（205B，305B）的基底半导体材料的中心部分（213B，313B）。因此，通过使用单个半导体合金（107,207,307,407），可以单独提高不同导电类型的晶体管（120A，120B）的性能。

4. 发明申请

WO2009108366A2 A SEMICONDUCTOR DEVICE COMPRISING A METAL GATE STACK OF REDUCED HEIGHT AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含降低高度的金属栅极堆叠的半导体器件及其形成方法
公开(公告)号：WO2009108366A2
公开(公告)日：2009-09-03
申请号：PCT/US2009/001283
申请日：2009-02-27
申请人： ADVANCED MICRO DEVICES, INC. , BEYER, Sven , STEPHAN, Rolf , TRENTZSCH, Martin , PRESS, Patrick
发明人： BEYER, Sven , STEPHAN, Rolf , TRENTZSCH, Martin , PRESS, Patrick
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7843 , H01L29/7848
摘要： By providing a CMP stop layer in a metal gate stack (160), the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas (152), thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material (161) may be positioned more closely to the channel region substantially without deteriorating gate conductivity.
摘要翻译：通过在金属栅极堆叠（160）中设置CMP停止层，在深层漏极和源极区域（152）的定义之后，其初始高度可被有效地降低，从而为形成高应力电介质材料提供了增强的工艺条件。因此，电介质材料（161）可以基本上不更改栅极导电性而更靠近沟道区。

5. 发明公开

EP1905068A2 TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING AVERTICAL DOPANT PROFILE 审中-公开
标题翻译：用于减少硅化物不均匀通过调整AVERTIKALEN掺杂物质简介技术
公开(公告)号：EP1905068A2
公开(公告)日：2008-04-02
申请号：EP06770831.3
申请日：2006-05-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WIRBELEIT, Frank , BROWN, David , PRESS, Patrick
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By modifying the vertical dopant concentration in deep drain and source regions, the reaction behavior during the formation of metal suicide regions 217 may be controlled. For this purpose, an increased dopant concentration is formed around a target depth (Xs) for the metal suicide interface, thereby reducing the reaction speeds and thus improving the uniformity of the resulting metal suicide interface.

6. 发明公开

EP2070112A2 A TRANSISTOR HAVING A LOCALLY PROVIDED METAL SILICIDE REGION IN CONTACT AREAS AND A METHOD OF FORMING THE TRANSISTOR 审中-公开
标题翻译：与LOCAL METALLSILICIDBEREICH接触区域内的及其制造方法晶体管晶体管
公开(公告)号：EP2070112A2
公开(公告)日：2009-06-17
申请号：EP07837528.4
申请日：2007-08-29
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BEYER, Sven , PRESS, Patrick , FEUDEL, Thomas
IPC分类号： H01L21/768 , H01L21/285 , H01L21/336
CPC分类号： H01L21/823418 , H01L21/28052 , H01L21/28518 , H01L21/76877 , H01L21/76883 , H01L21/823412 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823871 , H01L29/41725 , H01L29/665 , H01L29/66507 , H01L29/7842 , H01L29/7845 , H01L29/7848
摘要： By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.

7. 发明申请

WO2010062385A1 MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS 审中-公开
标题翻译：具有均质硅胶端部的多栅极晶体管
公开(公告)号：WO2010062385A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/006276
申请日：2009-11-25
申请人： GLOBALFOUNDRIES INC. , BEYER, Sven , PRESS, Patrick , GIEDIGKEIT, Rainer , HOENTSCHEL, Jan
发明人： BEYER, Sven , PRESS, Patrick , GIEDIGKEIT, Rainer , HOENTSCHEL, Jan
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795
摘要： In a multiple gate transistor, the plurality of fins of the drain or source (211) of the transistor (200) are electrically connected to each other by means of a common contact element (243), wherein enhanced uniformity of the corresponding contact regions (235) may be accomplished by an enhanced silicidation process sequence. For this purpose, the fins may be embedded into a dielectric material (230) in which an appropriate contact opening (230A) may be formed to expose end faces (210F) of the fins (210), which may then act as silicidation surface areas.
摘要翻译：在多栅极晶体管中，晶体管（200）的漏极或源极（211）的多个散热片通过公共接触元件（243）彼此电连接，其中相应的接触区域（ 235）可以通过增强的硅化工艺顺序完成。为此，翅片可嵌入介电材料（230）中，其中可以形成适当的接触开口（230A）以暴露翅片（210）的端面（210F），其然后可以作为硅化表面区域。

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